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Miller" , Eric Dumazet , Paolo Abeni , Qingfang Deng , SkyLake Huang , Matthias Brugger , AngeloGioacchino Del Regno Subject: Re: [PATCH v2] net: phy: add driver for MediaTek SoC built-in GE PHYs Message-ID: <20230424183755.3fac65b0@kernel.org> In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-7.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, 22 Apr 2023 13:36:58 +0100 Daniel Golle wrote: > Some of MediaTek's Filogic SoCs come with built-in gigabit Ethernet > PHYs which require calibration data from the SoC's efuse. > Despite the similar design the driver doesn't share any code with the > existing mediatek-ge.c, so add support for these PHYs by introducing a > new driver for only MediaTek's ARM64 SoCs. Andrew, Heiner, how do you feel about this driver? Daniel, is it high prio for you to get it into 6.4 or 6.5 is okay? I'm trying to get a read on whether we should merge it because it's kind of on the goal line for this merge window. If nobody feels strongly we can do this the traditional way - I'll just complain about RCT, hence kicking it back out into the field :)