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References: <20230424112523.1436926-1-angelogioacchino.delregno@collabora.com> <20230424112523.1436926-5-angelogioacchino.delregno@collabora.com>
In-Reply-To: <20230424112523.1436926-5-angelogioacchino.delregno@collabora.com>
From:   Chen-Yu Tsai <wenst@chromium.org>
Date:   Tue, 25 Apr 2023 16:25:25 +0800
Message-ID: <CAGXv+5GX1CqH4OEoL7tQ9bherzXOVpJrNGrSYQj4Oh3ecUJh3Q@mail.gmail.com>
Subject: Re: [PATCH v2 4/4] arm64: dts: mediatek: cherry: Enable PCI-Express
 ports for WiFi
To:     AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>
Cc:     matthias.bgg@gmail.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org, kernel@collabora.com
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On Mon, Apr 24, 2023 at 7:25=E2=80=AFPM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> On the Cherry platform, a MT7621 WiFi+Bluetooth combo is connected
> over PCI-Express (for WiFi) and USB (for BT): enable the PCIe ports
> to enable enumerating this chip.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@coll=
abora.com>
> Tested-by: Chen-Yu Tsai <wenst@chromium.org>
> ---
>  .../boot/dts/mediatek/mt8195-cherry.dtsi      | 25 +++++++++++++++++++
>  1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64=
/boot/dts/mediatek/mt8195-cherry.dtsi
> index adbda4dccdd5..eca5df85fe33 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi
> @@ -565,6 +565,13 @@ flash@0 {
>         };
>  };
>
> +&pcie1 {
> +       status =3D "okay";
> +
> +       pinctrl-names =3D "default";
> +       pinctrl-0 =3D <&pcie1_pins_default>;
> +};
> +
>  &pio {
>         mediatek,rsel-resistance-in-si-unit;
>         pinctrl-names =3D "default";
> @@ -959,6 +966,24 @@ pins-vreg-en {
>                 };
>         };
>
> +       pcie0_pins_default: pcie0-default-pins {
> +               pins-bus {
> +                       pinmux =3D <PINMUX_GPIO19__FUNC_WAKEN>,
> +                                <PINMUX_GPIO20__FUNC_PERSTN>,
> +                                <PINMUX_GPIO21__FUNC_CLKREQN>;
> +                                bias-pull-up;
> +               };
> +       };

I think we should remove this. We can add it later with the actual device
that has NVMe.

Otherwise,

Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>

> +       pcie1_pins_default: pcie1-default-pins {
> +               pins-bus {
> +                       pinmux =3D <PINMUX_GPIO22__FUNC_PERSTN_1>,
> +                                <PINMUX_GPIO23__FUNC_CLKREQN_1>,
> +                                <PINMUX_GPIO24__FUNC_WAKEN_1>;
> +                                bias-pull-up;
> +               };
> +       };
> +
>         pio_default: pio-default-pins {
>                 pins-wifi-enable {
>                         pinmux =3D <PINMUX_GPIO58__FUNC_GPIO58>;
> --
> 2.40.0
>