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Message-ID: <57b41394-fdc4-b185-94c9-9daac7a9b89b@ti.com>
Date:   Tue, 25 Apr 2023 18:06:45 +0530
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Subject: Re: [PATCH v14 5/8] arm64: dts: ti: k3-j721s2-common-proc-board: Add
 USB support
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To:     Roger Quadros <rogerq@kernel.org>, <nm@ti.com>, <afd@ti.com>,
        <vigneshr@ti.com>, <kristo@kernel.org>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <s-vadapalli@ti.com>,
        <vaishnav.a@ti.com>, ravi Gunasekaran <r-gunasekaran@ti.com>
CC:     <linux-arm-kernel@lists.infradead.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
References: <20230331090028.8373-1-r-gunasekaran@ti.com>
 <20230331090028.8373-6-r-gunasekaran@ti.com>
 <efe734a5-8d6f-b597-c4fd-bdf0879ed9c4@kernel.org>
From:   Ravi Gunasekaran <r-gunasekaran@ti.com>
In-Reply-To: <efe734a5-8d6f-b597-c4fd-bdf0879ed9c4@kernel.org>
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On 25/04/23 5:31 pm, Roger Quadros wrote:
> 
> 
> On 31/03/2023 12:00, Ravi Gunasekaran wrote:
>> From: Aswath Govindraju <a-govindraju@ti.com>
>>
>> The board uses lane 1 of SERDES for USB. Set the mux
>> accordingly.
>>
>> The USB controller and EVM supports super-speed for USB0
>> on the Type-C port. However, the SERDES has a limitation
>> that up to 2 protocols can be used at a time. The SERDES is
>> wired for PCIe, eDP and USB super-speed. It has been
>> chosen to use PCIe and eDP as default. So restrict
>> USB0 to high-speed mode.
>>
>> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
>> Signed-off-by: Matt Ranostay <mranostay@ti.com>
>> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
>> ---
>> I had reviewed this patch in the v5 series [0].
>> Since I'm taking over upstreaming this series, I removed the self
>> Reviewed-by tag.
>>

[...]

>> * No change
>>
>>  .../dts/ti/k3-j721s2-common-proc-board.dts    | 23 +++++++++++++++++++
>>  1 file changed, 23 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
>> index 1afefaf3f974..5c4ffb8124ca 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
>> @@ -147,6 +147,12 @@
>>  			J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */
>>  		>;
>>  	};
>> +
>> +	main_usbss0_pins_default: main-usbss0-pins-default {
>> +		pinctrl-single,pins = <
>> +			J721S2_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AG25) TIMER_IO1.USB0_DRVVBUS */
> 
> What about USB0_ID pin?
> 

The pin (AC9) for USB0_ID signal is not multiplexed with any other signals.
Please see Page 51 in [0].

>> +		>;
>> +	};
>>  };
>>  

[...]

>> +
>> +&usb0 {
>> +	dr_mode = "otg";
>> +	maximum-speed = "high-speed";
> 
> Why is super-speed not possible?
> I understood that SERDES lane 1 can be used for USB super-speed.

The SerDes on J721S2 can simultaneously support only two protocols.
By default PCIe and DP will be supported. Due to this, USB is configured
in high-speed and this does not require any SerDes lane configuration.

> 
>> +};
>> +
>>  &mcu_mcan0 {
>>  	status = "okay";
>>  	pinctrl-names = "default";
> 
> cheers,
> -roger

[0] https://www.ti.com/lit/gpn/TDA4AL-Q1 

-- 
Regards,
Ravi