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[209.85.166.171]) by smtp.gmail.com with ESMTPSA id m30-20020a056638271e00b00411bd20d4cbsm1704894jav.121.2023.04.25.08.07.18 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 25 Apr 2023 08:07:18 -0700 (PDT) Received: by mail-il1-f171.google.com with SMTP id e9e14a558f8ab-32ec968434eso87515ab.0 for ; Tue, 25 Apr 2023 08:07:18 -0700 (PDT) X-Received: by 2002:a05:6e02:1d96:b0:32a:dc6a:3b97 with SMTP id h22-20020a056e021d9600b0032adc6a3b97mr320927ila.0.1682435237664; Tue, 25 Apr 2023 08:07:17 -0700 (PDT) MIME-Version: 1.0 References: <1682412128-1913-1-git-send-email-quic_vnivarth@quicinc.com> In-Reply-To: <1682412128-1913-1-git-send-email-quic_vnivarth@quicinc.com> From: Doug Anderson Date: Tue, 25 Apr 2023 08:07:05 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH] spi: spi-geni-qcom: Correct CS_TOGGLE bit in SPI_TRANS_CFG To: Vijaya Krishna Nivarthi Cc: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, broonie@kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org, quic_msavaliy@quicinc.com, mka@chromium.org, swboyd@chromium.org, quic_vtanuku@quicinc.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Tue, Apr 25, 2023 at 1:42=E2=80=AFAM Vijaya Krishna Nivarthi wrote: > > The CS_TOGGLE bit when set is supposed to instruct FW to > toggle CS line between words. The driver with intent of > disabling this behaviour has been unsetting BIT(0). This has > not caused any trouble so far because the original BIT(1) > is untouched and BIT(0) likely wasn't being used. > > Correct this to prevent a potential future bug. > > Signed-off-by: Vijaya Krishna Nivarthi > --- > drivers/spi/spi-geni-qcom.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c > index ba7be50..8a7d1c2 100644 > --- a/drivers/spi/spi-geni-qcom.c > +++ b/drivers/spi/spi-geni-qcom.c > @@ -35,7 +35,7 @@ > #define CS_DEMUX_OUTPUT_SEL GENMASK(3, 0) > > #define SE_SPI_TRANS_CFG 0x25c > -#define CS_TOGGLE BIT(0) > +#define CS_TOGGLE BIT(1) Looks right to me from the datasheet I have access to. It's definitely specified in an odd way on the datasheet, which lists bit 1 as this, bit 2 and 3 as reserved, but bit 0 is absent. ...but seems like this is really supposed to be 1. I guess this never mattered because all we ever did was clear the bit at init time and it must have already been cleared? ...and, of course, on many Chromebooks we moved to just using a GPIO... Fixes: 561de45f72bd ("spi: spi-geni-qcom: Add SPI driver support for GENI based QUP") Reviewed-by: Douglas Anderson