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Date:   Wed, 26 Apr 2023 07:59:27 -0500
From:   Nishanth Menon <nm@ti.com>
To:     Siddharth Vadapalli <s-vadapalli@ti.com>
CC:     <vigneshr@ti.com>, <kristo@kernel.org>, <robh+dt@kernel.org>,
        <krzysztof.kozlowski@linaro.org>,
        <krzysztof.kozlowski+dt@linaro.org>, <afd@ti.com>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>, <srk@ti.com>
Subject: Re: [RFC PATCH 1/2] arm64: dts: ti: k3-j721s2-main: Add main CPSW2G
 devicetree node
Message-ID: <20230426125927.itfd76cpvy32zur7@scrimmage>
References: <20230426105718.118806-1-s-vadapalli@ti.com>
 <20230426105718.118806-2-s-vadapalli@ti.com>
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On 16:27-20230426, Siddharth Vadapalli wrote:
> From: Kishon Vijay Abraham I <kishon@ti.com>
> 
> TI's J721S2 SoC has a MAIN CPSW2G instance of the CPSW Ethernet Switch.
> Add devicetree node for it.
> 
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 69 ++++++++++++++++++++++
>  1 file changed, 69 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index 6629b2989180..14dfef7b0758 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -51,6 +51,12 @@ usb_serdes_mux: mux-controller@0 {
>  			mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
>  		};
>  
> +		phy_gmii_sel_cpsw: phy@34 {
> +			compatible = "ti,am654-phy-gmii-sel";
> +			reg = <0x34 0x4>;
> +			#phy-cells = <1>;
> +		};


See this thread: https://lore.kernel.org/all/76da0b98-3274-b047-db11-ecabc117ae11@ti.com/

[...]

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D