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From:   "Bouska, Zdenek" <zdenek.bouska@siemens.com>
To:     Thomas Gleixner <tglx@linutronix.de>,
        Will Deacon <will@kernel.org>,
        Catalin Marinas <catalin.marinas@arm.com>
CC:     "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "Kiszka, Jan" <jan.kiszka@siemens.com>,
        "linux-rt-users@vger.kernel.org" <linux-rt-users@vger.kernel.org>,
        Nishanth Menon <nm@ti.com>, Puranjay Mohan <p-mohan@ti.com>
Subject: Re: Unfair qspinlocks on ARM64 without LSE atomics => 3ms delay in
 interrupt handling
Thread-Topic: Unfair qspinlocks on ARM64 without LSE atomics => 3ms delay in
 interrupt handling
Thread-Index: AQHZeDcurMHHnME6s0CFTE/AvBQiT68+HAKAgACwhUQ=
Date:   Thu, 27 Apr 2023 09:38:59 +0000
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 <87pm7qxrg6.ffs@tglx>
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> Why is this interrupt handling specific? Just because it's the place=0A=
> where you observed it?=0A=
Yes.=0A=
=0A=
> So if that helps, then this needs to be addressed globaly and not with=0A=
> some crude hack in the interrupt handling code.=0A=
I just wrote, what helps for me. I didn't mean it as a proposal for merge.=
=0A=
Sorry for confusion.=0A=
=0A=
I tried using Will's cpu_relax() implementation [1] everywhere but I was no=
t =0A=
successful with that yet. ARM64's VDSO makes it complicating and even=0A=
if I left original cpu_relax() just in VDSO, Linux did not boot for me.=0A=
=0A=
Thank you all!=0A=
=0A=
[1] https://lore.kernel.org/lkml/20170728092831.GA24839@arm.com/=0A=
=0A=
Zdenek Bouska=0A=
=0A=
--=0A=
Siemens, s.r.o=0A=
Siemens Advanta Development=