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From:   Heiko Stuebner <heiko@sntech.de>
To:     Rob Herring <robh+dt@kernel.org>,
        Nicolas Frattaroli <frattaroli.nicolas@gmail.com>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Peter Geis <pgwipeout@gmail.com>
Cc:     Heiko Stuebner <heiko@sntech.de>, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org,
        linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2] arm64: dts: rockchip: fix nEXTRST on SOQuartz
Date:   Thu, 27 Apr 2023 11:58:08 +0200
Message-Id: <168258947019.413434.3793815124340047357.b4-ty@sntech.de>
In-Reply-To: <20230421152610.21688-1-frattaroli.nicolas@gmail.com>
References: <20230421152610.21688-1-frattaroli.nicolas@gmail.com>
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On Fri, 21 Apr 2023 17:26:10 +0200, Nicolas Frattaroli wrote:
> In pre-production prototypes (of which I only know one person
> having one, Peter Geis), GPIO0 pin A5 was tied to the SDMMC
> power enable pin on the CM4 connector. On all production models,
> this is not the case; instead, this pin is used for the nEXTRST
> signal, and the SDMMC power enable pin is always pulled high.
> 
> Since everyone currently using the SOQuartz device trees will
> want this change, it is made to the tree without splitting the
> trees into two separate ones of which users will then inevitably
> choose the wrong one.
> 
> [...]

Applied, thanks!

[1/1] arm64: dts: rockchip: fix nEXTRST on SOQuartz
      commit: e5d8752e957872a844ed46736b15f30b08af6591

As fix for 6.4

Best regards,
-- 
Heiko Stuebner <heiko@sntech.de>