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From:   Balsam CHIHI <bchihi@baylibre.com>
Date:   Thu, 27 Apr 2023 16:08:13 +0200
Message-ID: <CAGuA+oprz06WS0reC1Edqr1fMn-TjSrCgoO_M54JYQ4x8UnTOg@mail.gmail.com>
Subject: Re: [PATCH 0/4] Add LVTS support for mt8192
To:     =?UTF-8?B?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= 
        <nfraprado@collabora.com>
Cc:     Chen-Yu Tsai <wenst@chromium.org>, daniel.lezcano@linaro.org,
        angelogioacchino.delregno@collabora.com, rafael@kernel.org,
        amitk@kernel.org, rui.zhang@intel.com, matthias.bgg@gmail.com,
        robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
        rdunlap@infradead.org, ye.xingchen@zte.com.cn,
        p.zabel@pengutronix.de, linux-pm@vger.kernel.org,
        linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
        khilman@baylibre.com, james.lo@mediatek.com,
        rex-bc.chen@mediatek.com, Alexandre Bailon <abailon@baylibre.com>,
        Alexandre Mergnat <amergnat@baylibre.com>
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On Thu, Apr 27, 2023 at 1:20=E2=80=AFAM N=C3=ADcolas F. R. A. Prado
<nfraprado@collabora.com> wrote:
>
> On Tue, Apr 25, 2023 at 01:28:39PM +0200, Balsam CHIHI wrote:
> > On Tue, Apr 25, 2023 at 12:00=E2=80=AFPM Chen-Yu Tsai <wenst@chromium.o=
rg> wrote:
> > >
> > > On Tue, Apr 25, 2023 at 6:21=E2=80=AFAM N=C3=ADcolas F. R. A. Prado
> > > <nfraprado@collabora.com> wrote:
> > > >
> > > > On Tue, Mar 28, 2023 at 02:20:24AM +0200, Balsam CHIHI wrote:
> > > > > On Sat, Mar 25, 2023 at 5:33=E2=80=AFAM Chen-Yu Tsai <wenst@chrom=
ium.org> wrote:
> > > > > >
> > > > > > On Wed, Mar 22, 2023 at 8:48=E2=80=AFPM Balsam CHIHI <bchihi@ba=
ylibre.com> wrote:
> [..]
> > > > >
> > > > > Hi Chen-Yu Tsai,
> > > > >
> > > > > Thank you very much for helping me testing this suggestion.
> > > > >
> > > > > Indeed, calibration data is stored differently in the mt8192 comp=
ared to mt8195.
> > > > > So, the mt8192's support will be delayed for now, to allow furthe=
r debugging.
> > > > >
> > > > > In the mean time, we will only continue to upstream the remaining
> > > > > mt8195's source code, so it will get full LVTS support.
> > > > > A new series will be submitted soon.
> > > >
> > > > Hi Balsam,
> > > >
> > > > like Chen-Yu mentioned, the calibration data is stored with 4 byte =
alignment for
> > > > MT8192, but the data that is split between non-contiguous bytes is =
for the
> > > > thermal controllers (called Resistor-Capacitor Calibration downstre=
am) not the
> > > > sensors. The controller calibration isn't currently handled in this=
 driver (and
> > > > downstream it also isn't used, since a current value is read from t=
he controller
> > > > instead), so we can just ignore those.
> > > >
> > > > The patch below adjusts the addresseses for the sensors and gives m=
e reasonable
> > > > reads, so the machine no longer reboots. Can you integrate it into =
your series?
> > >
> > > Not sure what I got wrong, but on my machine the VPU0 and VPU1 zone i=
nterrupts
> > > are still tripping excessively. The readings seem normal though. Spec=
ifically,
> > > it's bits 16 and 17 that are tripping.
> > >
> >
> > Hi Chen-Yu,
> >
> > Thank you for testing!
> >
> > As the readings are normal that proves that calibration data offsets
> > are correct.
> > would you like that I send the v2 of series to add mt8192 support?
> > Then we could deal with the interrupts later in a separate fix,
> > because the interrupt code in common for both SoC (mt8192 and mt8195)?
> >
> > Does N=C3=ADcolas also have tripping interrupts?
> > On my side, I've got no interrupts tripping on mt8195.
> >
> > Any other suggestions (a question for everyone)?
>
> Hi,
>
> sorry for the delay.
>
> Indeed the interrupts are constantly tripping on mt8192 here as well.
>
> I do not see the same bits as Chen-Yu mentioned however, I see
>
> LVTS_MONINTSTS =3D 0x08070000
>
> which corresponds to
>
>         Hot threshold on sense point 3
>         high to normal offset on sense point 2
>         high offset on sense point 2
>         low offset on sense point 2
>
> and it's the same on all controllers and domains here, which is weird. I =
noticed
> we have offset interrupts enabled even though we don't configure the valu=
es for
> those, but even after disabling them and clearing the status register, th=
e
> interrupts keep triggering and the status is the same, so for some reason
> LVTS_MONINT doesn't seem to be honored.
>
> I also tried using the filtered mode instead of immediate for the sensors=
, and
> that together with disabling the extra interrupts, got me a zeroed
> LVTS_MONINTSTS. However no interrupts seem to be triggered at all (nor
> LVTS_MONINTSTS updated) when the temperature goes over the configured one=
 in
> LVTS_HTHRE.
>
> I tried the driver on mt8195 (Tomato chromebook) as well, and it has the =
same
> LVTS_MONINTSTS =3D 0x08070000
> even though the interrupts aren't being triggered, but in fact I don't se=
e them
> triggering over the threshold either, so I suspect the irq number might b=
e
> incorrectly described in the DT there.
>
> Do either of you have it working correctly on mt8195?
>
> Anyway, I'll keep digging and reply here when I find a solution.

Hi N=C3=ADcolas,

Thank your for your time testing and investigating the interrupt issues!

I only have an mt8195 based board (i1200-demo), and I could not
trigger any interrupt on it.
I whish that MediaTek could reply to this thread to give us more
information (I avoid disclosing MediaTek's internal information).
And now, it's clear that mt8192 interrupts does work at least (but not
properly, may be we could fix it at driver level).

It's been a couple of days since I sent a v2 of the series that adds
LVTS support for mt8192 SoC (+ Suspend and Resume, + Doc update):
"https://lore.kernel.org/all/20230425133052.199767-1-bchihi@baylibre.com/".
I wish that it will be applied very soon, then we could patch the core driv=
er.

My colleagues "Alexandre Mergnat (amergnat@baylibre.com)" and
"Alexandre Bailon (abailon@baylibre.com)" are now part of this
project.
Please let them know of future information.

Thanks again for suggesting solutions!

Best regards,
Balsam

>
> Thanks,
> N=C3=ADcolas