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Date:   Thu, 27 Apr 2023 16:06:08 -0400
From:   Hugo Villeneuve <hugo@hugovil.com>
To:     Fabio Estevam <festevam@gmail.com>
Cc:     Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        NXP Linux Team <linux-imx@nxp.com>,
        Hugo Villeneuve <hvilleneuve@dimonoff.com>,
        devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
        linux-kernel@vger.kernel.org
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Subject: Re: [PATCH] imx8mn-var-som: dts: fix PHY detection bug by adding
 deassert delay
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On Thu, 27 Apr 2023 17:00:41 -0300
Fabio Estevam <festevam@gmail.com> wrote:

> Hi Hugo,
> 
> On Thu, Apr 27, 2023 at 4:56 PM Hugo Villeneuve <hugo@hugovil.com> wrote:
> >
> > From: Hugo Villeneuve <hvilleneuve@dimonoff.com>
> >
> > While testing the ethernet interface on a symphony carrier
> > board using an imx8mn SOM with an onboard PHY (EC hardware
> > configuration), the ethernet PHY is not detected.
> >
> > The device tree in Variscite custom linux git repository uses the
> > following property:
> >
> >     phy-reset-post-delay = <20>;
> >
> > Add a new property 'reset-deassert-us' of 20ms to have the same delay
> > inside the ethphy handle.
> 
> Which Ethernet PHY does this board use?
> 
> What does its datasheet recommend?

Hi Fabio,
it uses a ADIN1300 PHY.

The datasheet indicate that the "Management interface active (t4)" state is reached at most 5ms after the reset signal is deasserted.

Hugo.

-- 
Hugo Villeneuve <hugo@hugovil.com>