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Date:   Fri, 28 Apr 2023 08:49:48 +0300
From:   Tony Lindgren <tony@atomide.com>
To:     "Kumar, Udit" <u-kumar1@ti.com>
Cc:     nm@ti.com, vigneshr@ti.com, kristo@kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org,
        linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org, m-chawdhry@ti.com, n-francis@ti.com
Subject: Re: [EXTERNAL] Re: [PATCH 1/5] arm64: dts: ti: k3-j7200: Add general
 purpose timers
Message-ID: <20230428054948.GI14287@atomide.com>
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 <20230427080049.GH14287@atomide.com>
 <24ea8982-e2ab-d58d-dedd-f51703d0bb92@ti.com>
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* Kumar, Udit <u-kumar1@ti.com> [230427 10:09]:
> Hi Tony
> 
> On 4/27/2023 1:30 PM, Tony Lindgren wrote:
> > Hi,
> > 
> > * Udit Kumar <u-kumar1@ti.com> [230426 10:38]:
> > > There are 20 general purpose timers on j7200 that can be used for things
> > > like PWM using pwm-omap-dmtimer driver. There are also additional ten
> > > timers in the MCU domain.
> > ...
> > 
> > ....
> > Oh so also the MCU timers now have interrupts, nice. Can you please check
> > if what we have in the comments the other SoCs in the dtsi files for MCU
> > timers not having routable interrupts is correct?
> 
> checked for AM65 and AM64, looks these SOC follow different IT map wrt J7200
> 
> On J7200 reading TRM
> 
> https://www.ti.com/lit/pdf/spruiu1
> 
> Section 9.4.3.1.2 GIC500 SPI Interrupt Map, table Table 9-109.
> 
> MCU_TIMER0_INTR_PEND_0 (848) to MCU_TIMER9_INTR_PEND_0 (857)
> 
> looks to be available for A core.

OK thanks a lot for checking it.

> > Also, should the MCU timers be still tagged with status = "reserved"?
> Will mark status as  reserved

OK thanks,

Tony