Received: by 2002:a05:6358:9144:b0:117:f937:c515 with SMTP id r4csp2821524rwr; Fri, 28 Apr 2023 17:05:54 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6Hl9Y5f2/iuWSRnYBKbiX9vf/KRlaIyLCvKDiqvVTZxMRHWekhDVvzYxja1NkdOxv168DV X-Received: by 2002:a17:90a:45:b0:247:9c7d:523a with SMTP id 5-20020a17090a004500b002479c7d523amr3846163pjb.4.1682726754380; Fri, 28 Apr 2023 17:05:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1682726754; cv=none; d=google.com; s=arc-20160816; b=PHYDCatR/CIaMpecMBJJuZuMOpppLeJ7DgYsQbeYhXnJiMC1ez0juzjEGJtFals0Qv 5c5l/G+tfpi/jopxMUjsBej2RnKx4lQ4hvqyMvcuRDnzNlt2iGHeOtvN8/dIqb923dnA KcL6Cp5TyHr3xbbbOO+5iFqJuoRyIf83REjVI7+0vhz6j8/+z+hwTKbATLPphMq/4T0O hHuNjaxy4z1HCAhuwziaezZTHkslPV0oHQVdsaT3lDV7NPxOz7LlIb1q85VI3WbxR64p SgWDOGdI3SA5/s3kMSeCRs8lgwNkNIaDYYGW2RK8tKdkrhRZdCJ1qQ3Uj2xt3CuEeHRF 0qRQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=wV4LdEJ2ofwpa9JtcSJW3D1ZqHtuyZ1wracfC5aYXyg=; b=h5iBdb38t2YUnae8S45ED2Ho7zq7Q7EOgF9jQATehIyjNr2HMVAmSILwzq8fHLKOD/ YOlwMIlckkeHhCwD2oLno7kQxB4cYTZBP88vxXz7Lm6l/uEcG1DtgipGL6lgbXx4frRT ALjWC0e0WjrFGXZjVtBDhv6i0DJaWbNXSm3DpFqagdjIy1wSAoGjLGq1c0lxJggKFwpZ OoI61qCUGl+iJLVPkj4lnXGpeTEMP3nD1IWXz8INde0QzRAfvj6bih5m45RQsrMXIOLg 6UJiN10szl/1ukNJU7FBl7IEuwSa52Vqlk7ACk11ksJtYFXnA1q58uXiJUqgRmKabc+i 5/Bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=B47rvZvp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id e10-20020a63690a000000b00524ea64ba6esi17746666pgc.530.2023.04.28.17.05.41; Fri, 28 Apr 2023 17:05:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=B47rvZvp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1347085AbjD1XqM (ORCPT + 99 others); Fri, 28 Apr 2023 19:46:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347075AbjD1Xpx (ORCPT ); Fri, 28 Apr 2023 19:45:53 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03B9059E4; Fri, 28 Apr 2023 16:45:48 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33SNiOYR018675; Fri, 28 Apr 2023 23:45:41 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=wV4LdEJ2ofwpa9JtcSJW3D1ZqHtuyZ1wracfC5aYXyg=; b=B47rvZvpK0GwoDfCHVs//s0/kmMN7fxUBEtkQVYod+UFR+KEYd8N+OHGGFBJD7FoOBp7 cWPpg8Nlsd7kPQ5wvnGU50ktIurJgRUn05aowUcivYma4/mWYtfQt57tiFzw66kEleCp uloYC6OWe7HUpstfcJPLDtAEFc8JxJ4nNpnuzkATa2x/CdYA77l1aRdm0oXJrGWQ11PO aDbpixeFK8A7i+EXnZRZ3W1iMQ3DIN9qL+rC3NmI9fQAmkFkmeQaY8l1uVt+VN2TvOgr K/RUvKkrk6uVjzuSPPxbCmIR+62QZr8UQFDiEHTFJGuk7BCLX/FhQVBvvZCkZP5KP1X+ /g== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3q8abptb41-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Apr 2023 23:45:41 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 33SNjef5015680 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 28 Apr 2023 23:45:40 GMT Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 28 Apr 2023 16:45:39 -0700 From: Kuogee Hsieh To: , , , , , , , , , , CC: Kuogee Hsieh , , , , , , Subject: [PATCH v2 7/7] drm/msm/dpu: calculate DSC encoder parameters dynamically Date: Fri, 28 Apr 2023 16:45:11 -0700 Message-ID: <1682725511-18185-8-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1682725511-18185-1-git-send-email-quic_khsieh@quicinc.com> References: <1682725511-18185-1-git-send-email-quic_khsieh@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 4vm5h3j3rUeMGu9EzRr4Em6jl3s4I-Ib X-Proofpoint-GUID: 4vm5h3j3rUeMGu9EzRr4Em6jl3s4I-Ib X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-28_08,2023-04-27_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 suspectscore=0 spamscore=0 impostorscore=0 mlxscore=0 bulkscore=0 malwarescore=0 clxscore=1015 adultscore=0 priorityscore=1501 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304280199 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org During DSC preparation, add run time calculation to figure out what usage modes, split mode and merge mode, is going to be setup. Signed-off-by: Kuogee Hsieh --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 56 ++++++++++++++++------------- 1 file changed, 31 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 2fdacf1..3d18642 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -529,17 +529,9 @@ void dpu_encoder_helper_split_config( bool dpu_encoder_use_dsc_merge(struct drm_encoder *drm_enc) { struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); - int i, intf_count = 0, num_dsc = 0; + struct msm_display_topology *topology = &dpu_enc->topology; - for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++) - if (dpu_enc->phys_encs[i]) - intf_count++; - - /* See dpu_encoder_get_topology, we only support 2:2:1 topology */ - if (dpu_enc->dsc) - num_dsc = 2; - - return (num_dsc > 0) && (num_dsc > intf_count); + return (topology->num_dsc > topology->num_intf); } static void dpu_encoder_get_topology( @@ -1861,41 +1853,55 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc, struct dpu_encoder_phys *enc_master = dpu_enc->cur_master; struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; - int this_frame_slices; + struct msm_display_topology *topology = &dpu_enc->topology; int intf_ip_w, enc_ip_w; - int dsc_common_mode; - int pic_width; + int dsc_common_mode = 0; u32 initial_lines; + int num_dsc = topology->num_dsc; + int num_intf = topology->num_intf; int i; - for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) { + for (i = 0; i < num_dsc; i++) { hw_pp[i] = dpu_enc->hw_pp[i]; hw_dsc[i] = dpu_enc->hw_dsc[i]; if (!hw_pp[i] || !hw_dsc[i]) { DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n"); return; - } + } } - dsc_common_mode = 0; - pic_width = dsc->pic_width; + intf_ip_w = dsc->pic_width; - dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL; if (enc_master->intf_mode == INTF_MODE_VIDEO) dsc_common_mode |= DSC_MODE_VIDEO; - this_frame_slices = pic_width / dsc->slice_width; - intf_ip_w = this_frame_slices * dsc->slice_width; - /* - * dsc merge case: when using 2 encoders for the same stream, - * no. of slices need to be same on both the encoders. + * If this encoder is driving more than one DSC encoder, they + * operate in tandem, same pic dimension needs to be used by + * each of them.(pp-split is assumed to be not supported) + * */ - enc_ip_w = intf_ip_w / 2; + enc_ip_w = intf_ip_w; + + intf_ip_w /= num_intf; + + if (num_dsc > 1) + dsc_common_mode |= DSC_MODE_SPLIT_PANEL; + + if (dpu_encoder_use_dsc_merge(&dpu_enc->base)) { + dsc_common_mode |= DSC_MODE_MULTIPLEX; + /* + * in dsc merge case: when using 2 encoders for the same + * stream, no. of slices need to be same on both the + * encoders. + */ + enc_ip_w = intf_ip_w / 2; + } + initial_lines = dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w); - for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) + for (i = 0; i < num_dsc; i++) dpu_encoder_dsc_pipe_cfg(dpu_enc, hw_dsc[i], hw_pp[i], dsc, dsc_common_mode, initial_lines); } -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project