Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753369AbXJAPWG (ORCPT ); Mon, 1 Oct 2007 11:22:06 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751661AbXJAPVz (ORCPT ); Mon, 1 Oct 2007 11:21:55 -0400 Received: from one.firstfloor.org ([213.235.205.2]:53133 "EHLO one.firstfloor.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751365AbXJAPVz (ORCPT ); Mon, 1 Oct 2007 11:21:55 -0400 Date: Mon, 1 Oct 2007 17:21:53 +0200 From: Andi Kleen To: Thomas Gleixner Cc: Andi Kleen , Mikhail Kshevetskiy , linux-kernel@vger.kernel.org Subject: Re: Fwd: x86_64 and AMD with C1E Message-ID: <20071001152153.GB19797@one.firstfloor.org> References: <20071001101532.025d652f@localhost> <20071001143225.GA19797@one.firstfloor.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.1i Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 713 Lines: 19 > So if the > number of hpet channels is greater/equal to the number of possible > CPUs it's perfectly fine and does not need IPI at all. That is only a stop gap then. I don't see this being generally true in the future. e.g. Intel announced SMT will be soon back so even a standard dual core would exceed it with current southbridges. Also I'm not sure but I suspect non Intel HPETs have less than three timers. Certainly they generally miss the 64bitness. -Andi - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/