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References: <20230426095805.15338-1-ddrokosov@sberdevices.ru> <20230426095805.15338-5-ddrokosov@sberdevices.ru>
In-Reply-To: <20230426095805.15338-5-ddrokosov@sberdevices.ru>
From:   Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Date:   Mon, 1 May 2023 20:53:37 +0200
Message-ID: <CAFBinCD2FKHsOiHyEDSLmTt2CE_5rUNXgyE4og=XS4Vf1ht5hg@mail.gmail.com>
Subject: Re: [PATCH v14 4/6] clk: meson: a1: add Amlogic A1 PLL clock
 controller driver
To:     Dmitry Rokosov <ddrokosov@sberdevices.ru>
Cc:     neil.armstrong@linaro.org, jbrunet@baylibre.com,
        mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, khilman@baylibre.com,
        jian.hu@amlogic.com, kernel@sberdevices.ru, rockosov@gmail.com,
        linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org
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On Wed, Apr 26, 2023 at 11:58=E2=80=AFAM Dmitry Rokosov
<ddrokosov@sberdevices.ru> wrote:
>
> Introduce PLL clock controller for Amlogic A1 SoC family.
> The clock unit is an APB slave module that is designed for generating all
> of the internal and system clocks.
> The SoC uses an external 24MHz crystal; there are 4 internal PLLs:
> SYS_PLL/HIFI_PLL/USB_PLL/(FIXPLL), these PLLs generate 27 clock sources.
>
> Signed-off-by: Jian Hu <jian.hu@amlogic.com>
> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>