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([2a02:810d:15c0:828:bafd:1283:b136:5f6a]) by smtp.gmail.com with ESMTPSA id hy13-20020a1709068a6d00b009606806b2fesm6457878ejc.217.2023.05.01.23.52.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 May 2023 23:52:29 -0700 (PDT) Message-ID: Date: Tue, 2 May 2023 08:52:27 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.1 Subject: Re: [PATCH v4 0/4] Enable multiple MCAN on AM62x Content-Language: en-US To: Judith Mendez , Chandrasekar Ramakrishnan , Wolfgang Grandegger , Marc Kleine-Budde , Krzysztof Kozlowski Cc: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-can@vger.kernel.org, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Schuyler Patton , Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Oliver Hartkopp , Simon Horman References: <20230501224624.13866-1-jm@ti.com> From: Krzysztof Kozlowski In-Reply-To: <20230501224624.13866-1-jm@ti.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 02/05/2023 00:46, Judith Mendez wrote: > On AM62x there is one MCAN in MAIN domain and two in MCU domain. > The MCANs in MCU domain were not enabled since there is no > hardware interrupt routed to A53 GIC interrupt controller. > Therefore A53 Linux cannot be interrupted by MCU MCANs. > > This solution instantiates a hrtimer with 1 ms polling interval > for MCAN device when there is no hardware interrupt and there is > poll-interval property in DTB MCAN node. The hrtimer generates a > recurring software interrupt which allows to call the isr. The isr > will check if there is pending transaction by reading a register > and proceed normally if there is. > > On AM62x, this series enables two MCU MCAN which will use the hrtimer > implementation. MCANs with hardware interrupt routed to A53 Linux > will continue to use the hardware interrupt as expected. > > Timer polling method was tested on both classic CAN and CAN-FD > at 125 KBPS, 250 KBPS, 1 MBPS and 2.5 MBPS with 4 MBPS bitrate > switching. > > Letency and CPU load benchmarks were tested on 3x MCAN on AM62x. > 1 MBPS timer polling interval is the better timer polling interval > since it has comparable latency to hardware interrupt with the worse > case being 1ms + CAN frame propagation time and CPU load is not > substantial. Latency can be improved further with less than 1 ms > polling intervals, howerver it is at the cost of CPU usage since CPU > load increases at 0.5 ms. > > Note that in terms of power, enabling MCU MCANs with timer-polling > implementation might have negative impact since we will have to wake > up every 1 ms whether there are CAN packets pending in the RX FIFO or > not. This might prevent the CPU from entering into deeper idle states > for extended periods of time. > > This patch series depends on 'Enable CAN PHY transceiver driver': > Link: https://lore.kernel.org/lkml/775ec9ce-7668-429c-a977-6c8995968d6e@app.fastmail.com/T/ > > v2: > Link: https://lore.kernel.org/linux-can/20230424195402.516-1-jm@ti.com/T/#t > > V1: > Link: https://lore.kernel.org/linux-can/19d8ae7f-7b74-a869-a818-93b74d106709@ti.com/T/#t > > RFC: > Link: https://lore.kernel.org/linux-can/52a37e51-4143-9017-42ee-8d17c67028e3@ti.com/T/#t > > Changes since v3: > - Wrong patch sent, resend correct patch series Sending patchsets every 10 minutes does not help us... Best regards, Krzysztof