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Message-ID: <6dd0ae37-9de9-c1fa-002c-b2b114b094a5@gmail.com>
Date:   Tue, 2 May 2023 11:24:01 -0700
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Subject: Re: [PATCH net 1/2] net: dsa: mt7530: fix corrupt frames using trgmii
 on 40 MHz XTAL MT7621
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To:     arinc9.unal@gmail.com, Sean Wang <sean.wang@mediatek.com>,
        Landen Chao <Landen.Chao@mediatek.com>,
        DENG Qingfang <dqfext@gmail.com>,
        Daniel Golle <daniel@makrotopia.org>,
        Andrew Lunn <andrew@lunn.ch>,
        Vladimir Oltean <olteanv@gmail.com>,
        "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
        Jakub Kicinski <kuba@kernel.org>,
        Paolo Abeni <pabeni@redhat.com>,
        Matthias Brugger <matthias.bgg@gmail.com>,
        AngeloGioacchino Del Regno 
        <angelogioacchino.delregno@collabora.com>,
        =?UTF-8?Q?Ren=c3=a9_van_Dorst?= <opensource@vdorst.com>
Cc:     =?UTF-8?B?QXLEsW7DpyDDnE5BTA==?= <arinc.unal@arinc9.com>,
        Bartel Eerdekens <bartel.eerdekens@constell8.be>,
        Richard van Schagen <richard@routerhints.com>,
        Richard van Schagen <vschagen@cs.com>,
        Frank Wunderlich <frank-w@public-files.de>,
        mithat.guner@xeront.com, erkin.bozoglu@xeront.com,
        netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
        linux-arm-kernel@lists.infradead.org,
        linux-mediatek@lists.infradead.org
References: <20230501121538.57968-1-arinc.unal@arinc9.com>
From:   Florian Fainelli <f.fainelli@gmail.com>
In-Reply-To: <20230501121538.57968-1-arinc.unal@arinc9.com>
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On 5/1/2023 5:15 AM, arinc9.unal@gmail.com wrote:
> From: Arınç ÜNAL <arinc.unal@arinc9.com>
> 
> The multi-chip module MT7530 switch with a 40 MHz oscillator on the
> MT7621AT, MT7621DAT, and MT7621ST SoCs forwards corrupt frames using
> trgmii.
> 
> This is caused by the assumption that MT7621 SoCs have got 150 MHz PLL,
> hence using the ncpo1 value, 0x0780.
> 
> My testing shows this value works on Unielec U7621-06, Bartel's testing
> shows it won't work on Hi-Link HLK-MT7621A and Netgear WAC104. All devices
> tested have got 40 MHz oscillators.
> 
> Using the value for 125 MHz PLL, 0x0640, works on all boards at hand. The
> definitions for 125 MHz PLL exist on the Banana Pi BPI-R2 BSP source code
> whilst 150 MHz PLL don't.
> 
> Forwarding frames using trgmii on the MCM MT7530 switch with a 25 MHz
> oscillator on the said MT7621 SoCs works fine because the ncpo1 value
> defined for it is for 125 MHz PLL.
> 
> Change the 150 MHz PLL comment to 125 MHz PLL, and use the 125 MHz PLL
> ncpo1 values for both oscillator frequencies.
> 
> Link: https://github.com/BPI-SINOVOIP/BPI-R2-bsp/blob/81d24bbce7d99524d0771a8bdb2d6663e4eb4faa/u-boot-mt/drivers/net/rt2880_eth.c#L2195
> Fixes: 7ef6f6f8d237 ("net: dsa: mt7530: Add MT7621 TRGMII mode support")
> Tested-by: Bartel Eerdekens <bartel.eerdekens@constell8.be>
> Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
> Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>

Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
-- 
Florian