Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754247AbXJBGT0 (ORCPT ); Tue, 2 Oct 2007 02:19:26 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1751866AbXJBGTT (ORCPT ); Tue, 2 Oct 2007 02:19:19 -0400 Received: from www.tglx.de ([62.245.132.106]:41590 "EHLO www.tglx.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751847AbXJBGTS (ORCPT ); Tue, 2 Oct 2007 02:19:18 -0400 Date: Tue, 2 Oct 2007 08:18:38 +0200 (CEST) From: Thomas Gleixner To: Andi Kleen cc: Arjan van de Ven , David Bahi , LKML , linux-rt-users@vger.kernel.org, Andrew Morton , Ingo Molnar , Gregory Haskins Subject: Re: nmi_watchdog fix for x86_64 to be more like i386 In-Reply-To: <200710020751.42994.ak@suse.de> Message-ID: References: <46FA4A800200006C000192FE@sinclair.provo.novell.com> <200710020007.09864.ak@suse.de> <200710020751.42994.ak@suse.de> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org Content-Length: 1499 Lines: 36 On Tue, 2 Oct 2007, Andi Kleen wrote: > > Agreed. > > > > I just got a x8664-hrt report, where I found the following oddity: > > > > 0: 1197 172881 IO-APIC-edge timer > > > > That's one of those infamous AMD C1E boxen. Strange, all my systems have > > IRQ#0 on CPU#0 and nowhere else. Any idea ? > > Hmm, in lowestpriority mode it would be possible that the APIC changes > the CPU to #1 once; but IRQ 0 is always set to fixed mode. Also even > if that happens you should have them all on 1. > > Maybe the chipset is just ignoring the IO-APIC configuration in this case? > > Is it always the same chipset? Is it seen on i386 too? > > The problem is really that if this happens it's more than the NMI watchdog > that is broken. If you don't run an additional APIC timer interrupt on CPU #0 > it's possible that CPU #0 won't schedule at all. > > The only workaround for chipsets ignoring IRQ affinity would be to keep > track on which CPU irq 0 happens and then restart APIC timer interrupts > on the others (or send IPIs) as needed. But that would be fairly ugly. The clock events code does handle this already. The broadcast interrupt can come in on any cpu. It's just the nmi watchdog which would be affected by that. tglx - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/