Received: by 2002:a05:6358:9144:b0:117:f937:c515 with SMTP id r4csp7392896rwr; Tue, 2 May 2023 14:07:51 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4Vv9iDZ02AQAAXbnwTyuaknv6bqYaWprldhvYrXBBBHzT8riwQm8uuH0++/L2XamYNOnkh X-Received: by 2002:a17:902:ec84:b0:1ab:1a5f:e061 with SMTP id x4-20020a170902ec8400b001ab1a5fe061mr588356plg.6.1683061671374; Tue, 02 May 2023 14:07:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683061671; cv=none; d=google.com; s=arc-20160816; b=0f+bYjSZJNKU8b6sZCl/VI4CxEpb4E0EL3LpkbedkaN0XG48dIJAiOxK9ROnsncTqe sh/oPv2uTYVtN9TkRhfU3AzbVjRiC6MWWR8+nkJl33NFR0PTWXjAgbFmDE0LWrx65vgO 5KrSvbRbtWT7TzLQBsY/MNMI704uJ2AhBDr5/Ipl7MxhmEWNJIHMA9w1weMAMZDaPs1e M136IzyxsuhYgJ52mCS/MKS6iJacHPi+izANX+bAgn67f44tbDZyKyWtlz3Je7dakX++ mTJow68Ws2yN1lTKb97KPRS5tr9X5dvcRFEASVwd2/fN883atFZn0BKMTs9WyrTc3G25 HKBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:message-id:date:subject:cc:to:from :dkim-signature; bh=G4fLH6tdDL+FxY4Uh5FL/iRjZOZqa0PyaTLaRGD7OLg=; b=wCPAlGKTCqocuRSVh7EmG4iEXx0XlPlXBuvJ6Q538Id44AJ6qkPndBgbU/BQhFK1VY S4N6XxBNc7ImNYraJ0u2gbQlQOIYU8A67XCRYi1ogeMK3ychLeI/qivzSbAPuQmhm3j3 B+D7wec+Ye/xKxXm7cd2s3kCsIBGv6j2IjZPVk6XUAQ17EX99l0QwhtTeTx8tD8SX27P v4hqcWuwyDIeZgUKwd4/UhF4UGhyy4wm1foGi7BDSohVqsp6pM4E2sayQlVn7zay3WQe o9rFDByBVrs8y6PYttbvOX+oWo7r8SOsXoeKBS2LHkX/j335i9vCpWlDyT20i1KL5nOn NBRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=is+HJDLV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 11-20020a170902c14b00b001a669006139si7708655plj.248.2023.05.02.14.07.32; Tue, 02 May 2023 14:07:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=is+HJDLV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229911AbjEBVD2 (ORCPT + 99 others); Tue, 2 May 2023 17:03:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229449AbjEBVD1 (ORCPT ); Tue, 2 May 2023 17:03:27 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A6177124; Tue, 2 May 2023 14:03:25 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 342K5SuD024453; Tue, 2 May 2023 21:03:16 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : mime-version : content-type; s=qcppdkim1; bh=G4fLH6tdDL+FxY4Uh5FL/iRjZOZqa0PyaTLaRGD7OLg=; b=is+HJDLVsbFSaDGgQLUsUjDeuctwAvflrogArLCaUc9W5YFdl+EKJW+lp4Vpj+5IAwC8 EhgK3l8CLLPRk5p/F3dk1M3il+6PZXjhLP3S0ruy1QFISPXqYjPGPQeOrZ8nJt9FMP/9 GGsjHxRCW1H+vZSpaG1GABx30gLNLqyVNZ0HiV0t+jVARJv+QFxHVzOdw+f14PA3jSZs YKqDHTeCsdSrD12i3wN0dUdXNJK3RxZR8Bdfou2FSizLbFiyyQ5XY+k/4RgUJLGjuLqX bkTCmoQLNFT/4VlcdQ7JFpu5TlOuX51ri2kYc8EQ+riwBniLRCA/8Hn6xAzosXBctyPQ RQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qays51m83-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 02 May 2023 21:03:15 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 342L3E5N019354 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 2 May 2023 21:03:14 GMT Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 2 May 2023 14:03:14 -0700 From: Kuogee Hsieh To: , , , , , , , , , , CC: Kuogee Hsieh , , , , , , Subject: [PATCH v3 0/7] add DSC 1.2 dpu supports Date: Tue, 2 May 2023 14:02:55 -0700 Message-ID: <1683061382-32651-1-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: udsnfO7veMSawhs7iSvunxL2OXnQEzYn X-Proofpoint-ORIG-GUID: udsnfO7veMSawhs7iSvunxL2OXnQEzYn X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-02_12,2023-04-27_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 spamscore=0 phishscore=0 malwarescore=0 adultscore=0 mlxscore=0 mlxlogscore=960 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2305020179 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series adds the DPU side changes to support DSC 1.2 encoder. This was validated with both DSI DSC 1.2 panel and DP DSC 1.2 monitor. The DSI and DP parts will be pushed later on top of this change. This seriel is rebase on [1], [2] and catalog fixes from [3]. [1]: https://patchwork.freedesktop.org/series/116851/ [2]: https://patchwork.freedesktop.org/series/116615/ [3]: https://patchwork.freedesktop.org/series/112332/ Abhinav Kumar (2): drm/msm/dpu: add dsc blocks for remaining chipsets in catalog drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets Kuogee Hsieh (5): drm/msm/dpu: add DPU_PINGPONG_DSC feature bit drm/msm/dpu: add DPU_PINGPONG_DSC bits into PP_BLK and PP_BLK_TE marcos drm/msm/dpu: add PINGPONG_NONE to disconnect DSC from PINGPONG drm/msm/dpu: add support for DSC encoder v1.2 engine drm/msm/dpu: separate DSC flush update out of interface drivers/gpu/drm/msm/Makefile | 1 + .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 19 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 8 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 26 +- .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 35 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 26 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 4 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 2 +- .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 2 +- .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 14 + .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 7 + .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 16 + .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 14 + .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 14 + drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 16 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 35 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 36 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 22 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 10 + drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 7 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 15 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c | 383 +++++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 9 +- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 7 +- 25 files changed, 649 insertions(+), 82 deletions(-) create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project