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References: <20230502010759.17282-1-aford173@gmail.com> <20230502010759.17282-8-aford173@gmail.com>
 <ba50c423-2678-3865-8f9a-907480c9870a@kontron.de>
In-Reply-To: <ba50c423-2678-3865-8f9a-907480c9870a@kontron.de>
From:   Adam Ford <aford173@gmail.com>
Date:   Wed, 3 May 2023 11:17:50 -0500
Message-ID: <CAHCN7x+ZQWspfiJVyrsJ=2E6OBya1o4vhBh9efxcjC09hv=Ziw@mail.gmail.com>
Subject: Re: [PATCH V3 7/7] drm: bridge: samsung-dsim: Let blanking calcuation
 work in non-burst mode
To:     Frieder Schrempf <frieder.schrempf@kontron.de>
Cc:     dri-devel@lists.freedesktop.org, marex@denx.de,
        aford@beaconembedded.com, Chen-Yu Tsai <wenst@chromium.org>,
        Andrzej Hajda <andrzej.hajda@intel.com>,
        Neil Armstrong <neil.armstrong@linaro.org>,
        Robert Foss <rfoss@kernel.org>,
        Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
        Jonas Karlman <jonas@kwiboo.se>,
        Jernej Skrabec <jernej.skrabec@gmail.com>,
        David Airlie <airlied@gmail.com>,
        Daniel Vetter <daniel@ffwll.ch>,
        Inki Dae <inki.dae@samsung.com>,
        Jagan Teki <jagan@amarulasolutions.com>,
        Marek Szyprowski <m.szyprowski@samsung.com>,
        linux-kernel@vger.kernel.org
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On Wed, May 3, 2023 at 10:52=E2=80=AFAM Frieder Schrempf
<frieder.schrempf@kontron.de> wrote:
>
> On 02.05.23 03:07, Adam Ford wrote:
> > The blanking calculation currently uses burst_clk_rate for calculating
> > the settings. Since it's possible to use this in non-burst mode, it's
> > possible that where won't be burst_clk_rate.  Instead, cache the
>
> "possible that burst_clk_rate is 0"
>
> > clock rate configured from of samsung_dsim_set_pll and use it instead.
> >
> > Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Chen-Yu Tsai <=
wenst@chromium.org>
>
> Maybe this patch should be squashed into patch 6/7 as otherwise
> burst_clk_rate could be 0 here causing bisection issues?

I thought about squashing them and I went back and forth on that.
Since there are some other minor edits in this series, I can push a V4
with these squashed.

>
> Apart from that:
>
> Tested on Kontron BL i.MX8MM with SN65DSI84 and ADV7535 bridges.
>

Thank you for testing this series.

> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
>

adam
> > ---
> >  drivers/gpu/drm/bridge/samsung-dsim.c | 4 +++-
> >  include/drm/bridge/samsung-dsim.h     | 1 +
> >  2 files changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/br=
idge/samsung-dsim.c
> > index 53099461cdc2..1dc913db2cb3 100644
> > --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> > +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> > @@ -652,6 +652,8 @@ static unsigned long samsung_dsim_set_pll(struct sa=
msung_dsim *dsi,
> >               reg =3D samsung_dsim_read(dsi, DSIM_STATUS_REG);
> >       } while ((reg & DSIM_PLL_STABLE) =3D=3D 0);
> >
> > +     dsi->hs_clock =3D fout;
> > +
> >       return fout;
> >  }
> >
> > @@ -960,7 +962,7 @@ static void samsung_dsim_set_display_mode(struct sa=
msung_dsim *dsi)
> >       u32 reg;
> >
> >       if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
> > -             int byte_clk_khz =3D dsi->burst_clk_rate / 1000 / 8;
> > +             int byte_clk_khz =3D dsi->hs_clock / 1000 / 8;>          =
 int hfp =3D (m->hsync_start - m->hdisplay) * byte_clk_khz / m->clock;
> >               int hbp =3D (m->htotal - m->hsync_end) * byte_clk_khz / m=
->clock;
> >               int hsa =3D (m->hsync_end - m->hsync_start) * byte_clk_kh=
z / m->clock;
> > diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/sam=
sung-dsim.h
> > index 76ea8a1720cc..14176e6e9040 100644
> > --- a/include/drm/bridge/samsung-dsim.h
> > +++ b/include/drm/bridge/samsung-dsim.h
> > @@ -94,6 +94,7 @@ struct samsung_dsim {
> >
> >       u32 pll_clk_rate;
> >       u32 burst_clk_rate;
> > +     u32 hs_clock;
> >       u32 esc_clk_rate;
> >       u32 lanes;
> >       u32 mode_flags;