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Date:   Thu, 4 May 2023 19:04:07 +0200
From:   Maxime Ripard <maxime@cerno.tech>
To:     Dinh Nguyen <dinguyen@kernel.org>
Cc:     Michael Turquette <mturquette@baylibre.com>,
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Subject: Re: [PATCH v3 29/65] clk: socfpga: gate: Add a determine_rate hook
Message-ID: <tgtfisqxubin4cjj6q26fboirbcnjzcazt5y3m322lw5lskz6l@d3tgz4hdfnk2>
References: <20221018-clk-range-checks-fixes-v3-0-9a1358472d52@cerno.tech>
 <20221018-clk-range-checks-fixes-v3-29-9a1358472d52@cerno.tech>
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 <sjlp5ubnpvulgwhhymmfkmmobkgxacyqwagqozodkee3di2qik@3igj6k3zgbk6>
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Hi Dinh,

On Thu, Apr 27, 2023 at 02:09:48PM -0500, Dinh Nguyen wrote:
> Hi Maxime,
>=20
> On 4/25/23 09:48, Maxime Ripard wrote:
> > Hi Dinh,
> >=20
> > On Mon, Apr 24, 2023 at 01:32:28PM -0500, Dinh Nguyen wrote:
> > > On 4/4/23 05:11, Maxime Ripard wrote:
> > > > The SoCFGPA gate clock implements a mux with a set_parent hook, but
> > > > doesn't provide a determine_rate implementation.
> > > >=20
> > > > This is a bit odd, since set_parent() is there to, as its name impl=
ies,
> > > > change the parent of a clock. However, the most likely candidate to
> > > > trigger that parent change is a call to clk_set_rate(), with
> > > > determine_rate() figuring out which parent is the best suited for a
> > > > given rate.
> > > >=20
> > > > The other trigger would be a call to clk_set_parent(), but it's far=
 less
> > > > used, and it doesn't look like there's any obvious user for that cl=
ock.
> > > >=20
> > > > So, the set_parent hook is effectively unused, possibly because of =
an
> > > > oversight. However, it could also be an explicit decision by the
> > > > original author to avoid any reparenting but through an explicit ca=
ll to
> > > > clk_set_parent().
> > > >=20
> > > > The latter case would be equivalent to setting the flag
> > > > CLK_SET_RATE_NO_REPARENT, together with setting our determine_rate =
hook
> > > > to __clk_mux_determine_rate(). Indeed, if no determine_rate
> > > > implementation is provided, clk_round_rate() (through
> > > > clk_core_round_rate_nolock()) will call itself on the parent if
> > > > CLK_SET_RATE_PARENT is set, and will not change the clock rate
> > > > otherwise. __clk_mux_determine_rate() has the exact same behavior w=
hen
> > > > CLK_SET_RATE_NO_REPARENT is set.
> > > >=20
> > > > And if it was an oversight, then we are at least explicit about our
> > > > behavior now and it can be further refined down the line.
> > > >=20
> > > > Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> > > > ---
> > > >    drivers/clk/socfpga/clk-gate.c | 3 ++-
> > > >    1 file changed, 2 insertions(+), 1 deletion(-)
> > > >=20
> > > > diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/c=
lk-gate.c
> > > > index 32ccda960f28..cbba8462a09e 100644
> > > > --- a/drivers/clk/socfpga/clk-gate.c
> > > > +++ b/drivers/clk/socfpga/clk-gate.c
> > > > @@ -110,6 +110,7 @@ static unsigned long socfpga_clk_recalc_rate(st=
ruct clk_hw *hwclk,
> > > >    static struct clk_ops gateclk_ops =3D {
> > > >    	.recalc_rate =3D socfpga_clk_recalc_rate,
> > > > +	.determine_rate =3D __clk_mux_determine_rate,
> > > >    	.get_parent =3D socfpga_clk_get_parent,
> > > >    	.set_parent =3D socfpga_clk_set_parent,
> > > >    };
> > > > @@ -166,7 +167,7 @@ void __init socfpga_gate_init(struct device_nod=
e *node)
> > > >    	init.name =3D clk_name;
> > > >    	init.ops =3D ops;
> > > > -	init.flags =3D 0;
> > > > +	init.flags =3D CLK_SET_RATE_NO_REPARENT;
> > > >    	init.num_parents =3D of_clk_parent_fill(node, parent_name, SOCF=
PGA_MAX_PARENTS);
> > > >    	if (init.num_parents < 2) {
> > > >=20
> > >=20
> > > This patch broke SoCFPGA boot serial port. The characters are mangled.
> >=20
> > Do you have any other access to that board? If so, could you dump
> > clk_summary in debugfs with and without that patch?
> >=20
>=20
> That dump from the clk_summary are identical for both cases.

Thanks for testing

I'm a bit confused, there should be no difference in behaviour, and if
there was any difference I would expect the clock tree to be somewhat
different.

Could you still paste the clk_summary (and dmesg) output? Which UART
driver is being used?

Also, is there a way for me to test it somehow?

Thanks,
Maxime

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