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Message-ID: <457c35b5-aec4-1147-673f-947052b5f944@starfivetech.com>
Date:   Fri, 5 May 2023 09:38:38 +0800
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Subject: Re: [PATCH v3 0/3] Add JH7110 cpufreq support
To:     "Rafael J. Wysocki" <rafael@kernel.org>,
        Viresh Kumar <viresh.kumar@linaro.org>,
        Emil Renner Berthing <kernel@esmil.dk>,
        "Rob Herring" <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor@kernel.org>,
        "Paul Walmsley" <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>
CC:     Shengyu Qu <wiagn233@outlook.com>, <linux-pm@vger.kernel.org>,
        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-riscv@lists.infradead.org>
References: <20230421031431.23010-1-mason.huo@starfivetech.com>
Content-Language: en-US
From:   Mason Huo <mason.huo@starfivetech.com>
In-Reply-To: <20230421031431.23010-1-mason.huo@starfivetech.com>
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Hi Conor & Shengyu,

Thanks for your review, and is there any comments about these v3 patches?

Thanks
Mason

On 2023/4/21 11:14, Mason Huo wrote:
> The StarFive JH7110 SoC has four RISC-V cores,
> and it supports up to 4 cpu frequency loads.
> 
> This patchset adds the compatible strings into the allowlist
> for supporting the generic cpufreq driver on JH7110 SoC.
> Also, it enables the axp15060 pmic for the cpu power source.
> 
> The series has been tested on the VisionFive 2 boards which
> are equipped with JH7110 SoC and axp15060 pmic.
> 
> 
> This patchset is based on v6.3-rc4 with these patches applied:
> [1] ("Basic clock, reset & device tree support for StarFive JH7110 RISC-V SoC")
>     https://lore.kernel.org/all/20230401111934.130844-1-hal.feng@starfivetech.com/
> [2] ("Add X-Powers AXP15060 PMIC support")
>     https://lore.kernel.org/all/TY3P286MB2611A814E580C96DC6F187B798969@TY3P286MB2611.JPNP286.PROD.OUTLOOK.COM/
> 
> Changes since v2:
> - Fix the new blank line at EOF issue in dtsi.
> 
> Changes since v1:
> - Fix dts node naming issues.
> - Move clock properties of cpu node from <board>.dtsi to <soc>.dtsi.
> - Follow the alphabetical order to place the cpufreq dt allowlist.
> 
> ---
> v1: https://lore.kernel.org/all/20230411083257.16155-1-mason.huo@starfivetech.com/
> v2: https://lore.kernel.org/lkml/20230417063942.3141-1-mason.huo@starfivetech.com/
> 
> Mason Huo (3):
>   riscv: dts: starfive: Enable axp15060 pmic for cpufreq
>   cpufreq: dt-platdev: Add JH7110 SOC to the allowlist
>   riscv: dts: starfive: Add cpu scaling for JH7110 SoC
> 
>  .../jh7110-starfive-visionfive-2.dtsi         | 30 +++++++++++++++++
>  arch/riscv/boot/dts/starfive/jh7110.dtsi      | 33 +++++++++++++++++++
>  drivers/cpufreq/cpufreq-dt-platdev.c          |  2 ++
>  3 files changed, 65 insertions(+)
> 
> base-commit: 197b6b60ae7bc51dd0814953c562833143b292aa