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Date:   Fri, 5 May 2023 10:58:05 +0100
From:   Andre Przywara <andre.przywara@arm.com>
To:     Maksim Kiselev <bigunclemax@gmail.com>
Cc:     robh+dt@kernel.org,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
        Jernej Skrabec <jernej.skrabec@gmail.com>,
        Samuel Holland <samuel@sholland.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Cristian Ciocaltea <cristian.ciocaltea@collabora.com>,
        devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
        linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev,
        linux-kernel@vger.kernel.org
Subject: Re: [PATCH] riscv: dts: allwinner: d1: Add SPI0 controller node
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In-Reply-To: <20230505074701.1030980-1-bigunclemax@gmail.com>
References: <20230505074701.1030980-1-bigunclemax@gmail.com>
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On Fri,  5 May 2023 10:46:51 +0300
Maksim Kiselev <bigunclemax@gmail.com> wrote:

Hi Maksim,

thanks for sending a patch!

> Some boards form the MangoPi family (MQ\MQ-Dual\MQ-R) may have
> an optional SPI flash that connects to the SPI0 controller.
> This controller is already supported by sun8i-h3-spi driver.
> So let's add its DT node.

Interesting, I see SPI mentioned in the D1 platform support cover letter,
but indeed there is no DT node. From a quick glance at the manuals, it
looks like there are not quite the same, though: the D1/R528/T113s
mentions a SPI_SAMP_DL register @0x28, whereas the older IP has a SPI_CCR
register @0x24 - which is not mentioned in the newer manuals. The driver
relies on that clock control register, so it wouldn't really work
reliably, if that register is not there. It *might* work by pure chance
because of a particular setup or clock rate, though.

Samuel, did you investigate SPI support on the D1/T113s? I see it marked
as "WIP" in the Wiki status page, so where there any patches floating
around?


Regardless of that, one comment that would apply anyway:

> Signed-off-by: Maksim Kiselev <bigunclemax@gmail.com>
> ---
>  .../boot/dts/allwinner/sunxi-d1s-t113.dtsi    | 20 +++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> index 922e8e0e2c09..d2de211d67d7 100644
> --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
> @@ -108,6 +108,12 @@ rmii_pe_pins: rmii-pe-pins {
>  				function = "emac";
>  			};
>  
> +			/omit-if-no-ref/
> +			spi0_pins: spi0-pins {
> +				pins = "PC2", "PC3", "PC4", "PC5";
> +				function = "spi0";
> +			};
> +
>  			/omit-if-no-ref/
>  			uart1_pg6_pins: uart1-pg6-pins {
>  				pins = "PG6", "PG7";
> @@ -447,6 +453,20 @@ mmc2: mmc@4022000 {
>  			#size-cells = <0>;
>  		};
>  
> +		spi0: spi@4025000 {
> +			compatible = "allwinner,sun8i-h3-spi";

Even if it would be compatible, we need to use a more specific compatible
first, with the H3 one as a fallback:

			compatible = "allwinner,sun20i-d1-spi",
				     "allwinner,sun8i-h3-spi";

But that would require that the H3 is a strict subset of the D1 SPI IP.

Cheers,
Andre


> +			reg = <0x04025000 0x300>;
> +			interrupts = <SOC_PERIPHERAL_IRQ(15) IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
> +			clock-names = "ahb", "mod";
> +			dmas = <&dma 22>, <&dma 22>;
> +			dma-names = "rx", "tx";
> +			resets = <&ccu RST_BUS_SPI0>;
> +			status = "disabled";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +		};
> +
>  		usb_otg: usb@4100000 {
>  			compatible = "allwinner,sun20i-d1-musb",
>  				     "allwinner,sun8i-a33-musb";