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References: <20230505074701.1030980-1-bigunclemax@gmail.com> <20230505105805.548d1a1b@donnerap.cambridge.arm.com>
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From:   Maxim Kiselev <bigunclemax@gmail.com>
Date:   Fri, 5 May 2023 17:27:07 +0400
Message-ID: <CALHCpMi8=t1bMceTOfZjh7aKEQcEEpfeG4wi9pB=5o34Ca+N3w@mail.gmail.com>
Subject: Re: [PATCH] riscv: dts: allwinner: d1: Add SPI0 controller node
To:     Andre Przywara <andre.przywara@arm.com>
Cc:     robh+dt@kernel.org,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor@kernel.org>, Chen-Yu Tsai <wens@csie.org>,
        Jernej Skrabec <jernej.skrabec@gmail.com>,
        Samuel Holland <samuel@sholland.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Cristian Ciocaltea <cristian.ciocaltea@collabora.com>,
        devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
        linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev,
        linux-kernel@vger.kernel.org
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Hi Andre,

> From a quick glance at the manuals, it
> looks like there are not quite the same, though: the D1/R528/T113s
> mentions a SPI_SAMP_DL register @0x28, whereas the older IP has a SPI_CCR
> register @0x24 - which is not mentioned in the newer manuals. The driver
> relies on that clock control register, so it wouldn't really work
> reliably, if that register is not there.

Thank you for pointing this out. I missed this difference.
I actually have a board with T113 SoC, and it looks like writing to
SPI_CCR@0x24 does nothing.
And it doesn't affect access to connected SPI NOR flash (read\write
operations are fine).
But I completely agree with you that this difference should be handled
by the spi driver.