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Date:   Fri, 5 May 2023 16:28:54 +0000
From:   Charles Keepax <ckeepax@opensource.cirrus.com>
To:     Srinivas Goud <srinivas.goud@amd.com>
CC:     <broonie@kernel.org>, <linux-spi@vger.kernel.org>,
        <linux-kernel@vger.kernel.org>, <git@amd.com>,
        <gcnu.goud@gmail.com>
Subject: Re: [PATCH v2 2/2] spi: spi-cadence: Add support for Slave mode
Message-ID: <20230505162854.GF68926@ediswmail.ad.cirrus.com>
References: <1681825625-10265-1-git-send-email-srinivas.goud@amd.com>
 <1681825625-10265-3-git-send-email-srinivas.goud@amd.com>
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On Tue, Apr 18, 2023 at 07:17:05PM +0530, Srinivas Goud wrote:
> Currently SPI Cadence controller works only in Master mode.
> Updated interrupt handler for Full duplex transfer in Slave mode.
> Interrupt handler rely on the TX empty interrupt even for Slave mode
> transfer due to below HW limitation.
> 
> HW limitation:
> AR 65885 - SPI Controller Might Not Update RX_NEMPTY Flag, Showing
> Incorrect Status Of The Receive FIFO
> 
> SPI Slave mode works in the following manner:
> 1.      One transfer can be finished only after all transfer->len
> data been transferred to master device.
> 2.      Slave device only accepts transfer->len data. Any data longer
> than this from master device will be dropped. Any data shorter than
> this from master will cause SPI to be stuck due to the above behavior.
> 3.      The stale data present in RXFIFO will be dropped in unprepared
> hardware transfer function.
> 
> Signed-off-by: Srinivas Goud <srinivas.goud@amd.com>
> ---

This patch appears to cause longer SPI transactions to be
corrupted on my Zynq board. Still investigating but its not
immediately obvious to me what the problem is so any
suggestions/comments on how much longer transaction testing this
has had would be great. I am using the SPI in master mode and I
am not sure exactly what transaction size hits the problem yet.

Thanks,
Charles