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References: <20230427142934.55435-1-francesco@dolcini.it> <20230427142934.55435-4-francesco@dolcini.it>
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From:   Robert Foss <rfoss@kernel.org>
Date:   Fri, 5 May 2023 19:39:00 +0200
Message-ID: <CAN6tsi5fBur-WSd5xN-=yyFDGiUWEq-U9=xXbYRSqzdeo8CxLw@mail.gmail.com>
Subject: Re: [PATCH v1 3/9] drm/bridge: tc358768: fix PLL target frequency
To:     Francesco Dolcini <francesco@dolcini.it>
Cc:     Andrzej Hajda <andrzej.hajda@intel.com>,
        Neil Armstrong <neil.armstrong@linaro.org>,
        Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
        Jonas Karlman <jonas@kwiboo.se>,
        Jernej Skrabec <jernej.skrabec@gmail.com>,
        tomi.valkeinen@ideasonboard.com, dri-devel@lists.freedesktop.org,
        Francesco Dolcini <francesco.dolcini@toradex.com>,
        David Airlie <airlied@gmail.com>,
        Daniel Vetter <daniel@ffwll.ch>, linux-kernel@vger.kernel.org
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On Thu, Apr 27, 2023 at 4:32=E2=80=AFPM Francesco Dolcini <francesco@dolcin=
i.it> wrote:
>
> From: Francesco Dolcini <francesco.dolcini@toradex.com>
>
> Correctly compute the PLL target frequency, the current formula works
> correctly only when the input bus width is 24bit, actually to properly
> compute the PLL target frequency what is relevant is the bits-per-pixel
> on the DSI link.
>
> No regression expected since the DSI format is currently hard-coded as
> MIPI_DSI_FMT_RGB888.
>
> Fixes: ff1ca6397b1d ("drm/bridge: Add tc358768 driver")
> Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
> ---
>  drivers/gpu/drm/bridge/tc358768.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/tc358768.c b/drivers/gpu/drm/bridge/t=
c358768.c
> index e9e3f9e02bba..dba1bf3912f1 100644
> --- a/drivers/gpu/drm/bridge/tc358768.c
> +++ b/drivers/gpu/drm/bridge/tc358768.c
> @@ -146,6 +146,7 @@ struct tc358768_priv {
>
>         u32 pd_lines; /* number of Parallel Port Input Data Lines */
>         u32 dsi_lanes; /* number of DSI Lanes */
> +       u32 dsi_bpp; /* number of Bits Per Pixel over DSI */
>
>         /* Parameters for PLL programming */
>         u32 fbd;        /* PLL feedback divider */
> @@ -284,12 +285,12 @@ static void tc358768_hw_disable(struct tc358768_pri=
v *priv)
>
>  static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk)
>  {
> -       return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->pd_line=
s);
> +       return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->dsi_bpp=
);
>  }
>
>  static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk)
>  {
> -       return (u32)div_u64((u64)pclk * priv->pd_lines, priv->dsi_lanes);
> +       return (u32)div_u64((u64)pclk * priv->dsi_bpp, priv->dsi_lanes);
>  }
>
>  static int tc358768_calc_pll(struct tc358768_priv *priv,
> @@ -426,6 +427,7 @@ static int tc358768_dsi_host_attach(struct mipi_dsi_h=
ost *host,
>         priv->output.panel =3D panel;
>
>         priv->dsi_lanes =3D dev->lanes;
> +       priv->dsi_bpp =3D mipi_dsi_pixel_format_to_bpp(dev->format);
>
>         /* get input ep (port0/endpoint0) */
>         ret =3D -EINVAL;
> @@ -437,7 +439,7 @@ static int tc358768_dsi_host_attach(struct mipi_dsi_h=
ost *host,
>         }
>
>         if (ret)
> -               priv->pd_lines =3D mipi_dsi_pixel_format_to_bpp(dev->form=
at);
> +               priv->pd_lines =3D priv->dsi_bpp;
>
>         drm_bridge_add(&priv->bridge);
>
> --
> 2.25.1
>

Reviewed-by: Robert Foss <rfoss@kernel.org>