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From:   Adam Ford <aford173@gmail.com>
Date:   Fri, 5 May 2023 19:37:17 -0500
Message-ID: <CAHCN7xLJ8D3dkbdEtUFd5RSvt=V0Xjmus2MxSKyRPhGRMrH+LA@mail.gmail.com>
Subject: Re: [PATCH V2] arm64: dts: imx8mn: Fix video clock parents
To:     linux-arm-kernel@lists.infradead.org
Cc:     aford@beaconembedded.com, Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Shawn Guo <shawnguo@kernel.org>,
        Sascha Hauer <s.hauer@pengutronix.de>,
        Pengutronix Kernel Team <kernel@pengutronix.de>,
        Fabio Estevam <festevam@gmail.com>,
        NXP Linux Team <linux-imx@nxp.com>,
        Marek Vasut <marex@denx.de>, devicetree@vger.kernel.org,
        linux-kernel@vger.kernel.org
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On Sun, Apr 23, 2023 at 7:35=E2=80=AFAM Adam Ford <aford173@gmail.com> wrot=
e:
>
> There are a few clocks whose parents are set in mipi_dsi
> and mxsfb nodes, but these clocks are used by the disp_blk_ctrl
> power domain which may cause an issue when re-parenting, resuling
> in a disp_pixel clock having the wrong parent and wrong rate.
>
> Fix this by moving the assigned-clock-parents as associate clock
> assignments to the power-domain node to setup these clocks before
> they are enabled.
>
> Fixes: d825fb6455d5 ("arm64: dts: imx8mn: Add display pipeline components=
")
> Signed-off-by: Adam Ford <aford173@gmail.com>

Shawn,

Any chance this can get applied?  Without it, the 8MN video doesn't
have correct parents and therefore the wrong clock rates too.

adam
> ---
> V2:  Split this into a separate patch away from a series of DSIM changes.
>      No actual changes made to the patch.
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/=
dts/freescale/imx8mn.dtsi
> index bd84db550053..8be8f090e8b8 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -1069,13 +1069,6 @@ lcdif: lcdif@32e00000 {
>                                          <&clk IMX8MN_CLK_DISP_APB_ROOT>,
>                                          <&clk IMX8MN_CLK_DISP_AXI_ROOT>;
>                                 clock-names =3D "pix", "axi", "disp_axi";
> -                               assigned-clocks =3D <&clk IMX8MN_CLK_DISP=
_PIXEL_ROOT>,
> -                                                 <&clk IMX8MN_CLK_DISP_A=
XI>,
> -                                                 <&clk IMX8MN_CLK_DISP_A=
PB>;
> -                               assigned-clock-parents =3D <&clk IMX8MN_C=
LK_DISP_PIXEL>,
> -                                                        <&clk IMX8MN_SYS=
_PLL2_1000M>,
> -                                                        <&clk IMX8MN_SYS=
_PLL1_800M>;
> -                               assigned-clock-rates =3D <594000000>, <50=
0000000>, <200000000>;
>                                 interrupts =3D <GIC_SPI 5 IRQ_TYPE_LEVEL_=
HIGH>;
>                                 power-domains =3D <&disp_blk_ctrl IMX8MN_=
DISPBLK_PD_LCDIF>;
>                                 status =3D "disabled";
> @@ -1093,12 +1086,6 @@ mipi_dsi: dsi@32e10000 {
>                                 clocks =3D <&clk IMX8MN_CLK_DSI_CORE>,
>                                          <&clk IMX8MN_CLK_DSI_PHY_REF>;
>                                 clock-names =3D "bus_clk", "sclk_mipi";
> -                               assigned-clocks =3D <&clk IMX8MN_CLK_DSI_=
CORE>,
> -                                                 <&clk IMX8MN_CLK_DSI_PH=
Y_REF>;
> -                               assigned-clock-parents =3D <&clk IMX8MN_S=
YS_PLL1_266M>,
> -                                                        <&clk IMX8MN_CLK=
_24M>;
> -                               assigned-clock-rates =3D <266000000>, <24=
000000>;
> -                               samsung,pll-clock-frequency =3D <24000000=
>;
>                                 interrupts =3D <GIC_SPI 18 IRQ_TYPE_LEVEL=
_HIGH>;
>                                 power-domains =3D <&disp_blk_ctrl IMX8MN_=
DISPBLK_PD_MIPI_DSI>;
>                                 status =3D "disabled";
> @@ -1142,6 +1129,21 @@ disp_blk_ctrl: blk-ctrl@32e28000 {
>                                               "lcdif-axi", "lcdif-apb", "=
lcdif-pix",
>                                               "dsi-pclk", "dsi-ref",
>                                               "csi-aclk", "csi-pclk";
> +                               assigned-clocks =3D <&clk IMX8MN_CLK_DSI_=
CORE>,
> +                                                 <&clk IMX8MN_CLK_DSI_PH=
Y_REF>,
> +                                                 <&clk IMX8MN_CLK_DISP_P=
IXEL>,
> +                                                 <&clk IMX8MN_CLK_DISP_A=
XI>,
> +                                                 <&clk IMX8MN_CLK_DISP_A=
PB>;
> +                               assigned-clock-parents =3D <&clk IMX8MN_S=
YS_PLL1_266M>,
> +                                                        <&clk IMX8MN_CLK=
_24M>,
> +                                                        <&clk IMX8MN_VID=
EO_PLL1_OUT>,
> +                                                        <&clk IMX8MN_SYS=
_PLL2_1000M>,
> +                                                        <&clk IMX8MN_SYS=
_PLL1_800M>;
> +                               assigned-clock-rates =3D <266000000>,
> +                                                      <24000000>,
> +                                                      <594000000>,
> +                                                      <500000000>,
> +                                                      <200000000>;
>                                 #power-domain-cells =3D <1>;
>                         };
>
> --
> 2.39.2
>