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From:   Luca Weiss <luca@z3ntu.xyz>
To:     linux-arm-msm@vger.kernel.org,
        ~postmarketos/upstreaming@lists.sr.ht
Cc:     ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org,
        Matti =?ISO-8859-1?Q?Lehtim=E4ki?= <matti.lehtimaki@gmail.com>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Konrad Dybcio <konrad.dybcio@linaro.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
        Matti =?ISO-8859-1?Q?Lehtim=E4ki?= <matti.lehtimaki@gmail.com>
Subject: Re: [PATCH 5/6] ARM: dts: msm8226: Add tsens node and related nvmem cells
Date:   Sun, 07 May 2023 22:31:01 +0200
Message-ID: <2503068.irdbgypaU6@z3ntu.xyz>
In-Reply-To: <20230507201225.89694-6-matti.lehtimaki@gmail.com>
References: <20230507201225.89694-1-matti.lehtimaki@gmail.com>
 <20230507201225.89694-6-matti.lehtimaki@gmail.com>
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On Sonntag, 7. Mai 2023 22:12:23 CEST Matti Lehtim=E4ki wrote:
> Specify pre-parsed per-sensor calibration nvmem cells in the qfprom
> device node rather than parsing the whole data blob in the driver.

I haven't double checked all the qfprom offsets but since you verified it
twice on your side, I believe you ;)

Reviewed-by: Luca Weiss <luca@z3ntu.xyz>

>=20
> Signed-off-by: Matti Lehtim=E4ki <matti.lehtimaki@gmail.com>
> ---
>  arch/arm/boot/dts/qcom-msm8226.dtsi | 113 ++++++++++++++++++++++++++++
>  1 file changed, 113 insertions(+)
>=20
> diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi
> b/arch/arm/boot/dts/qcom-msm8226.dtsi index c34b8f3139ae..a0c3d25eea65
> 100644
> --- a/arch/arm/boot/dts/qcom-msm8226.dtsi
> +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi
> @@ -500,6 +500,34 @@ data-pins {
>  			};
>  		};
>=20
> +		tsens: thermal-sensor@fc4a9000 {
> +			compatible =3D "qcom,msm8226-tsens", "qcom,tsens-v0_1";
> +			reg =3D <0xfc4a9000 0x1000>, /* TM */
> +			      <0xfc4a8000 0x1000>; /* SROT */
> +			nvmem-cells =3D <&tsens_mode>,
> +				      <&tsens_base1>, <&tsens_base2>,
> +				      <&tsens_s0_p1>, <&tsens_s0_p2>,
> +				      <&tsens_s1_p1>, <&tsens_s1_p2>,
> +				      <&tsens_s2_p1>, <&tsens_s2_p2>,
> +				      <&tsens_s3_p1>, <&tsens_s3_p2>,
> +				      <&tsens_s4_p1>, <&tsens_s4_p2>,
> +				      <&tsens_s5_p1>, <&tsens_s5_p2>,
> +				      <&tsens_s6_p1>, <&tsens_s6_p2>;
> +			nvmem-cell-names =3D "mode",
> +					   "base1", "base2",
> +					   "s0_p1", "s0_p2",
> +					   "s1_p1", "s1_p2",
> +					   "s2_p1", "s2_p2",
> +					   "s3_p1", "s3_p2",
> +					   "s4_p1", "s4_p2",
> +					   "s5_p1", "s5_p2",
> +					   "s6_p1", "s6_p2";
> +			#qcom,sensors =3D <6>;
> +			interrupts =3D <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names =3D "uplow";
> +			#thermal-sensor-cells =3D <1>;
> +		};
> +
>  		restart@fc4ab000 {
>  			compatible =3D "qcom,pshold";
>  			reg =3D <0xfc4ab000 0x4>;
> @@ -510,6 +538,91 @@ qfprom: qfprom@fc4bc000 {
>  			reg =3D <0xfc4bc000 0x1000>;
>  			#address-cells =3D <1>;
>  			#size-cells =3D <1>;
> +
> +			tsens_base1: base1@1c1 {
> +				reg =3D <0x1c1 0x2>;
> +				bits =3D <5 8>;
> +			};
> +
> +			tsens_s0_p1: s0-p1@1c2 {
> +				reg =3D <0x1c2 0x2>;
> +				bits =3D <5 6>;
> +			};
> +
> +			tsens_s1_p1: s1-p1@1c4 {
> +				reg =3D <0x1c4 0x1>;
> +				bits =3D <0 6>;
> +			};
> +
> +			tsens_s2_p1: s2-p1@1c4 {
> +				reg =3D <0x1c4 0x2>;
> +				bits =3D <6 6>;
> +			};
> +
> +			tsens_s3_p1: s3-p1@1c5 {
> +				reg =3D <0x1c5 0x2>;
> +				bits =3D <4 6>;
> +			};
> +
> +			tsens_s4_p1: s4-p1@1c6 {
> +				reg =3D <0x1c6 0x1>;
> +				bits =3D <2 6>;
> +			};
> +
> +			tsens_s5_p1: s5-p1@1c7 {
> +				reg =3D <0x1c7 0x1>;
> +				bits =3D <0 6>;
> +			};
> +
> +			tsens_s6_p1: s6-p1@1ca {
> +				reg =3D <0x1ca 0x2>;
> +				bits =3D <4 6>;
> +			};
> +
> +			tsens_base2: base2@1cc {
> +				reg =3D <0x1cc 0x1>;
> +				bits =3D <0 8>;
> +			};
> +
> +			tsens_s0_p2: s0-p2@1cd {
> +				reg =3D <0x1cd 0x1>;
> +				bits =3D <0 6>;
> +			};
> +
> +			tsens_s1_p2: s1-p2@1cd {
> +				reg =3D <0x1cd 0x2>;
> +				bits =3D <6 6>;
> +			};
> +
> +			tsens_s2_p2: s2-p2@1ce {
> +				reg =3D <0x1ce 0x2>;
> +				bits =3D <4 6>;
> +			};
> +
> +			tsens_s3_p2: s3-p2@1cf {
> +				reg =3D <0x1cf 0x1>;
> +				bits =3D <2 6>;
> +			};
> +
> +			tsens_s4_p2: s4-p2@446 {
> +				reg =3D <0x446 0x2>;
> +				bits =3D <4 6>;
> +			};
> +
> +			tsens_s5_p2: s5-p2@447 {
> +				reg =3D <0x447 0x1>;
> +				bits =3D <2 6>;
> +			};
> +
> +			tsens_s6_p2: s6-p2@44e {
> +				reg =3D <0x44e 0x1>;
> +				bits =3D <1 6>;
> +			};
> +
> +			tsens_mode: mode@44f {
> +				reg =3D <0x44f 0x1>;
> +				bits =3D <5 3>;
> +			};
>  		};
>=20
>  		spmi_bus: spmi@fc4cf000 {