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Message-ID: <56489d3f1b23a90baf3ef024da09b4c8c02a2204.camel@icenowy.me>
Subject: Re: [PATCH 1/5] irqchip/sifive-plic: Support T-HEAD's C910 PLIC
From:   Icenowy Zheng <uwu@icenowy.me>
To:     Jisheng Zhang <jszhang@kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Marc Zyngier <maz@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Conor Dooley <conor+dt@kernel.org>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Albert Ou <aou@eecs.berkeley.edu>
Cc:     linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
        linux-riscv@lists.infradead.org, Guo Ren <guoren@kernel.org>
Date:   Mon, 08 May 2023 11:14:32 +0800
In-Reply-To: <20230507182304.2934-2-jszhang@kernel.org>
References: <20230507182304.2934-1-jszhang@kernel.org>
         <20230507182304.2934-2-jszhang@kernel.org>
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=E5=9C=A8 2023-05-08=E6=98=9F=E6=9C=9F=E4=B8=80=E7=9A=84 02:23 +0800=EF=BC=
=8CJisheng Zhang=E5=86=99=E9=81=93=EF=BC=9A
> The T-HEAD's C910 PLIC still needs the delegation bit settingto allow
> access from S-mode, but it doesn't need the edge quirk.

No, the PLIC controller seems to be the same between C906 and C910,
which has level/edge selectable via external signal.

See openc906 and openc910 repositories, especially the documents with
it: =E7=8E=84=E9=93=81C9{06,10}=E9=9B=86=E6=88=90=E6=89=8B=E5=86=8C.pdf .

In addition, such problem won't arise when the system uses only level-
triggered interrupts.

>=20
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
> =C2=A0.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0 | 4
> ++++
> =C2=A0drivers/irqchip/irq-sifive-plic.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 1 +
> =C2=A02 files changed, 5 insertions(+)
>=20
> diff --git a/Documentation/devicetree/bindings/interrupt-
> controller/sifive,plic-1.0.0.yaml
> b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-
> 1.0.0.yaml
> index f75736a061af..64b43a3c3748 100644
> --- a/Documentation/devicetree/bindings/interrupt-
> controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-
> controller/sifive,plic-1.0.0.yaml
> @@ -62,6 +62,10 @@ properties:
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0 - starfive,jh7110-plic
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0 - canaan,k210-plic
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - const: sif=
ive,plic-1.0.0
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - items:
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - enum:
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0 - thead,light-plic
> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - const: thead,c9=
10-plic
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - items:
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 - enum:
> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0 - allwinner,sun20i-d1-plic
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-
> sifive-plic.c
> index e1484905b7bd..71afa2a584d9 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -569,6 +569,7 @@ static int __init plic_init(struct device_node
> *node,
> =C2=A0}
> =C2=A0
> =C2=A0IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
> +IRQCHIP_DECLARE(thead_c910_plic, "thead,c910-plic", plic_init);
> =C2=A0IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for
> legacy systems */
> =C2=A0
> =C2=A0static int __init plic_edge_init(struct device_node *node,