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Message-ID: <7bf5a2c1-ae97-ae8c-5621-25e06d186a65@linaro.org>
Date:   Mon, 8 May 2023 09:48:18 +0200
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Subject: Re: [PATCH 2/3] arm64: dts: qcom: msm8996: correct MMCC clocks order
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To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <andersson@kernel.org>,
        Rob Herring <robh+dt@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Vinod Koul <vkoul@kernel.org>, linux-arm-msm@vger.kernel.org,
        devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
References: <20230507174516.264936-1-krzysztof.kozlowski@linaro.org>
 <20230507174516.264936-2-krzysztof.kozlowski@linaro.org>
From:   Konrad Dybcio <konrad.dybcio@linaro.org>
In-Reply-To: <20230507174516.264936-2-krzysztof.kozlowski@linaro.org>
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On 7.05.2023 19:45, Krzysztof Kozlowski wrote:
> Re-order the clocks for MMCC clock controller node to match the bindings (Linux
> driver takes by name):
> 
>   msm8996-mtp.dtb: clock-controller@8c0000: clock-names:1: 'gpll0' was expected
>   msm8996-mtp.dtb: clock-controller@8c0000: clock-names:2: 'gcc_mmss_noc_cfg_ahb_clk' was expected
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Konrad
>  arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index fe9e1cb12a73..718007cfb10e 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -939,16 +939,16 @@ mmcc: clock-controller@8c0000 {
>  			#power-domain-cells = <1>;
>  			reg = <0x008c0000 0x40000>;
>  			clocks = <&xo_board>,
> -				 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
>  				 <&gcc GPLL0>,
> +				 <&gcc GCC_MMSS_NOC_CFG_AHB_CLK>,
>  				 <&dsi0_phy 1>,
>  				 <&dsi0_phy 0>,
>  				 <&dsi1_phy 1>,
>  				 <&dsi1_phy 0>,
>  				 <&hdmi_phy>;
>  			clock-names = "xo",
> -				      "gcc_mmss_noc_cfg_ahb_clk",
>  				      "gpll0",
> +				      "gcc_mmss_noc_cfg_ahb_clk",
>  				      "dsi0pll",
>  				      "dsi0pllbyte",
>  				      "dsi1pll",