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charset=utf-8 Content-Disposition: inline In-Reply-To: <20230505093733.221922-3-angelogioacchino.delregno@collabora.com> X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Angelo, On Fri, May 05, 2023 at 11:37:33AM +0200, AngeloGioacchino Del Regno wrote: > Various MSDC core clocks, used for multiple MSDC controller instances, > share the same parent(s): in order to add parents selection in the > mtk-sd driver to achieve an accurate clock rate for all modes, remove > the CLK_SET_RATE_PARENT flag from all MSDC clocks for all SoCs: this > will make sure that a clk_set_rate() call performed for a clock on > a secondary controller will not change the rate of a common parent, > which would result in an overclock or underclock of one of the > controllers. > > Signed-off-by: AngeloGioacchino Del Regno > --- > drivers/clk/mediatek/clk-mt6765.c | 12 +++++------ > drivers/clk/mediatek/clk-mt6779.c | 18 ++++++++-------- > drivers/clk/mediatek/clk-mt7981-topckgen.c | 12 +++++------ > drivers/clk/mediatek/clk-mt7986-topckgen.c | 12 +++++------ > drivers/clk/mediatek/clk-mt8173-topckgen.c | 24 +++++++++++----------- > drivers/clk/mediatek/clk-mt8183.c | 16 +++++++-------- > drivers/clk/mediatek/clk-mt8186-topckgen.c | 12 +++++------ > drivers/clk/mediatek/clk-mt8188-topckgen.c | 16 +++++++-------- > drivers/clk/mediatek/clk-mt8192.c | 17 +++++++-------- > drivers/clk/mediatek/clk-mt8195-topckgen.c | 16 +++++++-------- This is missing clk-mt8365.c as well. Otherwise looks good to me: Reviewed-by: Markus Schneider-Pargmann Best, Markus