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[209.85.128.177]) by smtp.gmail.com with ESMTPSA id q188-20020a8180c5000000b0054f9e7fed7asm2413053ywf.137.2023.05.08.03.55.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 08 May 2023 03:55:40 -0700 (PDT) Received: by mail-yw1-f177.google.com with SMTP id 00721157ae682-559e317eef1so64016527b3.0; Mon, 08 May 2023 03:55:40 -0700 (PDT) X-Received: by 2002:a81:d510:0:b0:559:fad8:322f with SMTP id i16-20020a81d510000000b00559fad8322fmr11658525ywj.24.1683543339883; Mon, 08 May 2023 03:55:39 -0700 (PDT) MIME-Version: 1.0 References: <20230506141703.65605-1-contact@artur-rojek.eu> <20230506141703.65605-3-contact@artur-rojek.eu> In-Reply-To: <20230506141703.65605-3-contact@artur-rojek.eu> From: Geert Uytterhoeven Date: Mon, 8 May 2023 12:55:28 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 2/2] sh: dma: Correct the number of DMA channels in SH7709 To: Artur Rojek Cc: Yoshinori Sato , Rich Felker , John Paul Adrian Glaubitz , Rafael Ignacio Zurita , linux-sh@vger.kernel.org, linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT X-Spam-Status: No, score=-1.4 required=5.0 tests=BAYES_00, FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Sat, May 6, 2023 at 4:22 PM Artur Rojek wrote: > According to the PM, the DMAC found in SH7709 features only 4 channels. > > Signed-off-by: Artur Rojek Reviewed-by: Geert Uytterhoeven > --- a/arch/sh/drivers/dma/Kconfig > +++ b/arch/sh/drivers/dma/Kconfig > @@ -28,8 +28,9 @@ config SH_DMA_API > config NR_ONCHIP_DMA_CHANNELS > int > depends on SH_DMA > - default "4" if CPU_SUBTYPE_SH7750 || CPU_SUBTYPE_SH7751 || \ > - CPU_SUBTYPE_SH7750S || CPU_SUBTYPE_SH7091 > + default "4" if CPU_SUBTYPE_SH7709 || CPU_SUBTYPE_SH7750 || \ > + CPU_SUBTYPE_SH7751 || CPU_SUBTYPE_SH7750S || \ > + CPU_SUBTYPE_SH7091 > default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R || \ > CPU_SUBTYPE_SH7760 > default "12" if CPU_SUBTYPE_SH7723 || CPU_SUBTYPE_SH7780 || \ > @@ -37,8 +38,9 @@ config NR_ONCHIP_DMA_CHANNELS > default "6" > help > This allows you to specify the number of channels that the on-chip > - DMAC supports. This will be 4 for SH7750/SH7751/Sh7750S/SH7091 and 8 for the Might be a good opportunity to s/Sh7750S/SH7750S/ > - SH7750R/SH7751R/SH7760, 12 for the SH7723/SH7780/SH7785/SH7724, default is 6. > + DMAC supports. This will be 4 for SH7709/SH7750/SH7751/Sh7750S/SH7091 > + and 8 for the SH7750R/SH7751R/SH7760, 12 for the SH7723/SH7780/SH7785/SH7724, ... and sort the list for SoCs with 12 channels. > + default is 6. > > config SH_DMABRG > bool "SH7760 DMABRG support" Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds