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[2620:137:e000::1:20]) by mx.google.com with ESMTP id u12-20020a170903124c00b001ac8cd69347si1083289plh.179.2023.05.09.01.05.58; Tue, 09 May 2023 01:06:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=jZWAUgBy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234146AbjEIHmW (ORCPT + 99 others); Tue, 9 May 2023 03:42:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233970AbjEIHmV (ORCPT ); Tue, 9 May 2023 03:42:21 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2D4177EC0 for ; Tue, 9 May 2023 00:42:20 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B9CA4623BC for ; Tue, 9 May 2023 07:42:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E5DCEC433EF; Tue, 9 May 2023 07:42:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683618139; bh=YGlkJ3i9JNyLfqvHrSsT4y5Xrl4atadaw7GlOBqXwOQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=jZWAUgBy/xfsMImVidCfu67IbyOI8iWO+64EZiOq3T+4VVsfKPqL9Hpg2DYcIk+oe gWVC9U7RnwQ6Ckt+m0GnOOVU1oIMHfIyFYawKBq0WfVdUAR5gHwzPaDl7ollRGbgnR 9ftoMLmXOwiBr5q8KMqcvH4ka3NOM+J3gYmXgkmkph5qMtPcaoVFGUKw9rySqjdLHG 5Jbjil1nwmDNLOcS2u93qnVdJ7g5vd/4Ug379uoWUfNbBDM0eZUDzHqcAOZZyheJ7C flCx0udOljUdMslUF5AtdWZmaa6xc5KL2OxOL4LKyYVQUTQ8d3gDoozMInnNOPwMBD nm+gcRUya8oBA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pwHzE-00Dord-Ki; Tue, 09 May 2023 08:42:16 +0100 Date: Tue, 09 May 2023 08:42:09 +0100 Message-ID: <864jomne7i.wl-maz@kernel.org> From: Marc Zyngier To: Geert Uytterhoeven Cc: Russell King , Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 0/2] ARM/arm64: Mark all accessor functions inline In-Reply-To: References: User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: geert+renesas@glider.be, linux@armlinux.org.uk, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Geert, On Mon, 08 May 2023 17:05:17 +0100, Geert Uytterhoeven wrote: > > Hi all, > > This patch series adds missing "inline" keywords to the few perf > accessors that lack them. I'll get to that shortly. > > BTW, I tried converting my local timing code to the new unified system. > This works fine on arm64, but broke on arm32. Is read_pmccntr() > supposed to work on arm32? I get an undefined instruction exception on > Cortex A15 and A9. Before, my custom code used "mrc p15, 0, %0, c9, > c13, 0" (as is also used in arch/arm/kernel/perf_event_v7.c), for which > there is no accessor yet. You can only use this instruction on a CPU that implements PMUv3, which limits it to an ARMv8 implementation (either a 64bit CPU in 32bit mode, or something like an A32). A15 and A9 being firmly in the ARMv7 camp, they cannot make use of this (hence the UNDEF you're getting). Thanks, M. -- Without deviation from the norm, progress is not possible.