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[2620:137:e000::1:20]) by mx.google.com with ESMTP id d1-20020a621d01000000b00645e8c9e27esi2756186pfd.386.2023.05.09.10.34.42; Tue, 09 May 2023 10:34:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Sv6OIaJu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235151AbjEIRWh (ORCPT + 99 others); Tue, 9 May 2023 13:22:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37308 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234934AbjEIRWa (ORCPT ); Tue, 9 May 2023 13:22:30 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E99584699; Tue, 9 May 2023 10:22:28 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 349Ggc7l005734; Tue, 9 May 2023 17:22:25 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=N690EkHL2jERDbkzv9IJC+1w8aZCLf4RDqrFl417RdY=; b=Sv6OIaJuWMpQIU54UmjlAWc6IgDc+0D7qz4d221nNIWctTTAe8kyjPfJsp6lBWOU5nrY 0S3F5BEK6/HNKSDIOhmg10FFJQrIgJa6pLlSyzfVRQpd02lWDgBzYoim33y525U2hJK0 U9vavR1Y5kW6fHXY2/6BOfEUUmJsxp8S/vf6zjVJ47VBwAdW+qDxX3B9O0hRwV3VPKPb H6f7Qy47Maj2J4pg6KIP5pnOqWoQJhS3LtAAkiDDm41TPjTWF+Ya+lDPkHD0dDbJyI7F UAE1mSR+ECG0xt5a2vPizYE6TkyNABEOqzgEChdUrYiJ6XQim5J9SBZNhwnk8qWNgxtM zg== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qf77ktf6v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 May 2023 17:22:25 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 349HMPT5023879 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 9 May 2023 17:22:25 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 9 May 2023 10:22:20 -0700 From: Taniya Das To: Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Andy Gross , Michael Turquette CC: Bjorn Andersson , Konrad Dybcio , Taniya Das , , , , , , Subject: [PATCH V4 3/3] arm64: dts: qcom: sm8450: Add video clock controller Date: Tue, 9 May 2023 22:51:48 +0530 Message-ID: <20230509172148.7627-4-quic_tdas@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230509172148.7627-1-quic_tdas@quicinc.com> References: <20230509172148.7627-1-quic_tdas@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 44pGCFyUs_FLiQedIVevmAHeqeDxGg9o X-Proofpoint-ORIG-GUID: 44pGCFyUs_FLiQedIVevmAHeqeDxGg9o X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-09_10,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 suspectscore=0 adultscore=0 mlxlogscore=961 lowpriorityscore=0 phishscore=0 impostorscore=0 spamscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305090144 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add device node for video clock controller on Qualcomm SM8450 platform. Signed-off-by: Taniya Das --- Changes since V3: - None. Changes since V2: - No changes. Changes since V1: - No changes. arch/arm64/boot/dts/qcom/sm8450.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 595533aeafc4..00ff8efa53c7 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -756,6 +756,18 @@ "usb3_phy_wrapper_gcc_usb30_pipe_clk"; }; + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8450-videocc"; + reg = <0 0x0aaf0000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + gpi_dma2: dma-controller@800000 { compatible = "qcom,sm8450-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells = <3>; -- 2.17.1