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([2a02:810d:15c0:828:c175:a0f9:6928:8c9d]) by smtp.gmail.com with ESMTPSA id bf18-20020a0564021a5200b004bd6e3ed196sm1532628edb.86.2023.05.10.00.12.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 May 2023 00:12:21 -0700 (PDT) Message-ID: <603c177d-07c7-4cb4-da53-0e1a11ee8828@linaro.org> Date: Wed, 10 May 2023 09:12:20 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH V4 1/3] dt-bindings: clock: qcom: Add SM8450 video clock controller Content-Language: en-US To: Taniya Das , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Andy Gross , Michael Turquette Cc: Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, quic_skakitap@quicinc.com, quic_jkona@quicinc.com References: <20230509172148.7627-1-quic_tdas@quicinc.com> <20230509172148.7627-2-quic_tdas@quicinc.com> From: Krzysztof Kozlowski In-Reply-To: <20230509172148.7627-2-quic_tdas@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 09/05/2023 19:21, Taniya Das wrote: > Add device tree bindings for the video clock controller on Qualcomm > SM8450 platform. > > Signed-off-by: Taniya Das > Reviewed-by: Rob Herring > --- > Changes since V3: > - None. > > Changes since V2: > - As per Stephen's comments drop clock-names to match how newer > qcom clk bindings are being done. > - Change the header file name as qcom,sm8450-videocc.h to match > latest upstream header files. > > Changes since V1: > - Change the properties order to keep reg after the compatible > property. > > .../bindings/clock/qcom,sm8450-videocc.yaml | 77 +++++++++++++++++++ > .../dt-bindings/clock/qcom,sm8450-videocc.h | 38 +++++++++ > 2 files changed, 115 insertions(+) > create mode 100644 Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > create mode 100644 include/dt-bindings/clock/qcom,sm8450-videocc.h > > diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > new file mode 100644 > index 000000000000..58e59065bb2a > --- /dev/null > +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml > @@ -0,0 +1,77 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/clock/qcom,sm8450-videocc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Video Clock & Reset Controller on SM8450 > + > +maintainers: > + - Taniya Das > + > +description: | > + Qualcomm video clock control module provides the clocks, resets and power > + domains on SM8450. > + > + See also:: include/dt-bindings/clock/qcom,videocc-sm8450.h > + > +properties: > + compatible: > + const: qcom,sm8450-videocc > + > + reg: > + maxItems: 1 > + > + clocks: > + items: > + - description: Video AHB clock from GCC > + - description: Board XO source Why the order is different than all other devices? Board XO is always first. Best regards, Krzysztof