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Wed, 10 May 2023 03:50:40 -0500 Received: from xhdsneeli40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Wed, 10 May 2023 03:50:36 -0500 From: Sarath Babu Naidu Gaddam To: , , , , , CC: , , , , , , , , , , Subject: [PATCH net-next V3 1/3] dt-bindings: net: xilinx_axienet: Introduce dmaengine binding support Date: Wed, 10 May 2023 14:20:29 +0530 Message-ID: <20230510085031.1116327-2-sarath.babu.naidu.gaddam@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230510085031.1116327-1-sarath.babu.naidu.gaddam@amd.com> References: <20230510085031.1116327-1-sarath.babu.naidu.gaddam@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT015:EE_|IA0PR12MB9045:EE_ X-MS-Office365-Filtering-Correlation-Id: 7de78640-2ce4-46a6-21ce-08db5133a2b7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2023 08:50:41.7368 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7de78640-2ce4-46a6-21ce-08db5133a2b7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB9045 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Radhey Shyam Pandey The axiethernet driver will use dmaengine framework to communicate with dma controller IP instead of built-in dma programming sequence. To request dma transmit and receive channels the axiethernet driver uses generic dmas, dma-names properties. Also to support the backward compatibility, use "dmas" property to identify as it should use dmaengine framework or legacy driver(built-in dma programming). At this point it is recommended to use dmaengine framework but it's optional. Once the solution is stable will make dmas as required properties. Signed-off-by: Radhey Shyam Pandey Signed-off-by: Sarath Babu Naidu Gaddam --- These changes are on top of below txt to yaml conversion discussion https://lore.kernel.org/all/20230308061223.1358637-1-sarath.babu.naidu.gaddam@amd.com/#Z2e.:20230308061223.1358637-1-sarath.babu.naidu.gaddam::40amd.com:1bindings:net:xlnx::2caxi-ethernet.yaml Changes in V3: 1) Reverted reg and interrupts property to support backward compatibility. 2) Moved dmas and dma-names properties from Required properties. Changes in V2: - None. --- .../devicetree/bindings/net/xlnx,axi-ethernet.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml index 80843c177029..9dfa1976e260 100644 --- a/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml +++ b/Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml @@ -122,6 +122,16 @@ properties: modes, where "pcs-handle" should be used to point to the PCS/PMA PHY, and "phy-handle" should point to an external PHY if exists. + dmas: + items: + - description: TX DMA Channel phandle and DMA request line number + - description: RX DMA Channel phandle and DMA request line number + + dma-names: + items: + - const: tx_chan0 + - const: rx_chan0 + required: - compatible - interrupts @@ -157,6 +167,8 @@ examples: clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>; phy-mode = "mii"; reg = <0x40c00000 0x40000>,<0x50c00000 0x40000>; + dmas = <&xilinx_dma 0>, <&xilinx_dma 1>; + dma-names = "tx_chan0", "rx_chan0"; xlnx,rxcsum = <0x2>; xlnx,rxmem = <0x800>; xlnx,txcsum = <0x2>; -- 2.25.1