Received: by 2002:a05:6358:9144:b0:117:f937:c515 with SMTP id r4csp7942245rwr; Wed, 10 May 2023 15:13:34 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7/Ob9qP/SPpuymL6VnzHzsANJZptvthli6BHOPQLNnIWL5GG41dmFzJ+NVvpY4QfiMyavx X-Received: by 2002:a17:902:cecf:b0:1ac:96e7:e97d with SMTP id d15-20020a170902cecf00b001ac96e7e97dmr8688527plg.67.1683756813798; Wed, 10 May 2023 15:13:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683756813; cv=none; d=google.com; s=arc-20160816; b=t2WSzruKNVhg281VlepzkbpmYPrGADGWzLAqx4FxYqERbCVNXJFiGIYGpDbsAauhPu Xqb2CXa1Uk3mVZf5rHJhN5LJHRj6kCmJq9JUS3nsmk9a6xcAZKFj5qmIBBAolPGeZT31 bte8Q8HMZ0VniAtU+Ck1UtxCqUhqzGA5OKpxulCvQUjHcKwcxagxEP4iX0dUrClSh6e9 X4GM+mxiWWwyFGdW+kMs/iMJjXOQzLftbQzlgHr8lqnoiJmwBbPfxrYJZMe+fs0SCEq9 PViyt9PUJHcfAYsPsdgEJ2BG1xwGzzQ4zkFrKQ6ynqYfDBoNEi015jjRZi8CF97PEO/8 z17w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=mmVwWdv8/CzN3Q4Inkjzuto4wX1saGV3DwfdN+CadxY=; b=Co8bdr2E7B/jQtEO9O7IqawdlPjsFNFSx5b88VD6KGPD/QfEz4CcGQAISrN9uKJ88G jerP2xZ5VnZvdl9jqoZx7YUOGQoFCJo2a5LE+1qDwm06f7x4glCREMe2augZuLkoUsvn VxiJQsAPW+lpmmX/JvXs4CaiZDv+FotD2m7j2WObYmQNpBYjLieRgX7MQWva2STIFlib qKX+K14dzOqczzchehDFFkJ0V/JJ68T5bz3IDRNr0lnOJV3I/KaUE9tR2ElQBHWK/9Yu WXYl+1LVqNhHXBHsZAzWmlpxf6oLBzw6oaTNnMzKktoJ/vsU5YPsXK+BxWHSlBbDXp7F As9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Ezf0aAAp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Return-Path: Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id jc12-20020a17090325cc00b001ac741db80asi2971468plb.236.2023.05.10.15.13.21; Wed, 10 May 2023 15:13:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=Ezf0aAAp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236358AbjEJWIH (ORCPT + 99 others); Wed, 10 May 2023 18:08:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236253AbjEJWIA (ORCPT ); Wed, 10 May 2023 18:08:00 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4AA9C30C1; Wed, 10 May 2023 15:07:59 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34AKnqqC003907; Wed, 10 May 2023 22:07:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=mmVwWdv8/CzN3Q4Inkjzuto4wX1saGV3DwfdN+CadxY=; b=Ezf0aAApou69LarfYAa85F4ya6bK0rM6feo5ZTrDXC+sXkVe63pHOFFh9gR686H9wAu1 SYZrjL9QnWq0V2vTzQ/+TKLZTIwpDhUSRZ+bFb1TyVbk/6vhn06Gsg0+2YoLDKcXAEbX 7EzcdHPSvWvl2ZHvdQ5YgG4yRJMESw+B9VT4LZlZujumIxV49ZjogznIIZCFbTzxuc8U fHBuwk/m1kIGE7bZMWRrp1F1MvoweTXw3Kzl3m9zB6381doi7JFgu+oZX1mHbnDIDBzK Rbp684lk6GKkw6PhAXuy2ve9kyPij5EHWrvvhhZ7Mo/5hHovyZEBv7sFs0P7u3NoAe6A bg== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qg79csmpu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 May 2023 22:07:51 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34AM7ogG006902 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 10 May 2023 22:07:50 GMT Received: from khsieh-linux1.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 10 May 2023 15:07:49 -0700 From: Kuogee Hsieh To: , , , , , , , , , , CC: Kuogee Hsieh , , , , , , , Subject: [PATCH v6 2/8] drm/msm/dpu: add DPU_PINGPONG_DSC feature bit for DPU < 7.0.0 Date: Wed, 10 May 2023 15:07:27 -0700 Message-ID: <1683756453-22050-3-git-send-email-quic_khsieh@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1683756453-22050-1-git-send-email-quic_khsieh@quicinc.com> References: <1683756453-22050-1-git-send-email-quic_khsieh@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: WXLF-ESniaYUJ9FB0D8N-L6Wz4Ref_2G X-Proofpoint-ORIG-GUID: WXLF-ESniaYUJ9FB0D8N-L6Wz4Ref_2G X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-10_04,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 mlxscore=0 suspectscore=0 bulkscore=0 spamscore=0 priorityscore=1501 mlxlogscore=655 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305100182 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org DPU < 7.0.0 requires the PINGPONG block to be involved during DSC setting up. Since DPU >= 7.0.0, enabling and starting the DSC encoder engine moved to INTF with the help of the flush mechanism. Add a DPU_PINGPONG_DSC feature bit to restrict the availability of dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_{enable,disable}() on the PINGPONG block to DPU < 7.0.0 hardware, as the registers are not available [in the PINGPONG block] on DPU 7.0.0 and higher anymore. Existing call-sites to these callbacks already skip calling into them if the function pointer is NULL. Add DPU_PINGPONG_DSC feature bit to all chipset with DPU < 7.0.0. changes in v6: -- split patches and rearrange to keep catalog related files at this patch Signed-off-by: Kuogee Hsieh --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 +++- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 82b58c6..78e4bf6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -76,13 +76,13 @@ (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) #define PINGPONG_SDM845_MASK \ - (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_TE)) + (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_TE) | BIT(DPU_PINGPONG_DSC)) #define PINGPONG_SDM845_TE2_MASK \ - (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) + (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2) | BIT(DPU_PINGPONG_DSC)) #define PINGPONG_SM8150_MASK \ - (BIT(DPU_PINGPONG_DITHER)) + (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) #define CTL_SC7280_MASK \ (BIT(DPU_CTL_ACTIVE_CFG) | \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index 6ee48f0..dc0a4da 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -144,7 +144,8 @@ enum { * @DPU_PINGPONG_TE2 Additional tear check block for split pipes * @DPU_PINGPONG_SPLIT PP block supports split fifo * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo - * @DPU_PINGPONG_DITHER, Dither blocks + * @DPU_PINGPONG_DITHER Dither blocks + * @DPU_PINGPONG_DSC PP ops functions required for DSC * @DPU_PINGPONG_MAX */ enum { @@ -153,6 +154,7 @@ enum { DPU_PINGPONG_SPLIT, DPU_PINGPONG_SLAVE, DPU_PINGPONG_DITHER, + DPU_PINGPONG_DSC, DPU_PINGPONG_MAX }; -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project