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Message-ID: <a6146d03-18d1-b1c6-cdbb-d3527cb9021a@linaro.org>
Date:   Thu, 11 May 2023 07:39:48 +0300
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Subject: Re: [PATCH v6 2/8] drm/msm/dpu: add DPU_PINGPONG_DSC feature bit for
 DPU < 7.0.0
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To:     Abhinav Kumar <quic_abhinavk@quicinc.com>,
        Kuogee Hsieh <quic_khsieh@quicinc.com>,
        dri-devel@lists.freedesktop.org, robdclark@gmail.com,
        sean@poorly.run, swboyd@chromium.org, dianders@chromium.org,
        vkoul@kernel.org, daniel@ffwll.ch, airlied@gmail.com,
        agross@kernel.org, andersson@kernel.org
Cc:     quic_jesszhan@quicinc.com, quic_sbillaka@quicinc.com,
        marijn.suijten@somainline.org, freedreno@lists.freedesktop.org,
        linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org
References: <1683756453-22050-1-git-send-email-quic_khsieh@quicinc.com>
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 <1a6109ae-7c83-c04e-60c9-dfca6b83d662@quicinc.com>
From:   Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
In-Reply-To: <1a6109ae-7c83-c04e-60c9-dfca6b83d662@quicinc.com>
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On 11/05/2023 07:38, Abhinav Kumar wrote:
> 
> 
> On 5/10/2023 9:29 PM, Dmitry Baryshkov wrote:
>> On 11/05/2023 01:07, Kuogee Hsieh wrote:
>>> DPU < 7.0.0 requires the PINGPONG block to be involved during
>>> DSC setting up. Since DPU >= 7.0.0, enabling and starting the DSC
>>> encoder engine moved to INTF with the help of the flush mechanism.
>>
>> Nit: was moved.
>>
>>> Add a DPU_PINGPONG_DSC feature bit to restrict the availability of
>>> dpu_hw_pp_setup_dsc() and dpu_hw_pp_dsc_{enable,disable}() on the
>>> PINGPONG block to DPU < 7.0.0 hardware, as the registers are not
>>> available [in the PINGPONG block] on DPU 7.0.0 and higher anymore.
>>
>> this looks good
>>
>>> Existing call-sites to these callbacks already skip calling into
>>> them if the function pointer is NULL.
>>
>> This is more relevant for patch 3 commit message.
>>
>>> Add DPU_PINGPONG_DSC feature
>>> bit to all chipset with DPU < 7.0.0.
>>
>> This is incorrect, as we do not change the catalog in this patch.
>>
> 
> Sorry but why not? The changes done to dpu_hw_catalog.c do exactly that.

Because the patch does not add this feature bit to any of the chipsets. 
I think the relevant patch was lost somewhere during the rework/rebase.


-- 
With best wishes
Dmitry