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Thu, 11 May 2023 05:00:46 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34B50PqP007411 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 11 May 2023 05:00:25 GMT Received: from nasanex01a.na.qualcomm.com (10.52.223.231) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 10 May 2023 22:00:24 -0700 Received: from nasanex01a.na.qualcomm.com ([fe80::efb2:2dda:c355:1de3]) by nasanex01a.na.qualcomm.com ([fe80::efb2:2dda:c355:1de3%12]) with mapi id 15.02.0986.042; Wed, 10 May 2023 22:00:24 -0700 From: "Sarthak Garg (QUIC)" To: Christoph Hellwig CC: "adrian.hunter@intel.com" , "ulf.hansson@linaro.org" , "linux-mmc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-msm@vger.kernel.org" , "Ram Prakash Gupta (QUIC)" , "Bhaskar Valaboju (QUIC)" , "Sachin Gupta (QUIC)" , "Pradeep Pragallapati (QUIC)" , "Sayali Lokhande (QUIC)" , Brian Norris , "Wolfram Sang" , Linus Walleij Subject: RE: [PATCH V1 1/2] mmc: core: Define new vendor ops to enable internal features Thread-Topic: [PATCH V1 1/2] mmc: core: Define new vendor ops to enable internal features Thread-Index: AQHZZLsSreM1n2UsG0iOAGSJueq9468bFEYAgA9GsjCAAHb4AP//nJxwgADjuYCAJTsTYA== Date: Thu, 11 May 2023 05:00:24 +0000 Message-ID: References: <20230401165723.19762-1-quic_sartgarg@quicinc.com> <20230401165723.19762-2-quic_sartgarg@quicinc.com> <53eda50111e2402e889bd690a0112ee1@quicinc.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.216.8.139] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: fkvlJ7lTMBMSgRr8zFHGHeMZ7aLa0Spc X-Proofpoint-ORIG-GUID: fkvlJ7lTMBMSgRr8zFHGHeMZ7aLa0Spc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-10_04,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxlogscore=999 mlxscore=0 adultscore=0 clxscore=1011 malwarescore=0 priorityscore=1501 phishscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305110041 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Thanks for your valuable comments. We didn't ignore the previous comments i= nstead we tried to address most of the comments by trying the suggested alt= ernatives as well but didn't see power improvement as compared to this feat= ure. Moreover we got the intuition that maintainability was the main concer= n hence we came up with this newer approach of hooks to limit the lines of = code in core layer. Every change was pushed earlier in the previous posts a= nd this time we just refactored the code and was about to push the series b= ut as per current discussion we'll be reviving the old discussion and try t= o close all the comments. Closing this thread now. > -----Original Message----- > From: Christoph Hellwig > Sent: Friday, April 14, 2023 6:46 PM > To: Sarthak Garg (QUIC) > Cc: Christoph Hellwig ; adrian.hunter@intel.com; > ulf.hansson@linaro.org; linux-mmc@vger.kernel.org; linux- > kernel@vger.kernel.org; linux-arm-msm@vger.kernel.org; Ram Prakash Gupta > (QUIC) ; Bhaskar Valaboju (QUIC) > ; Sachin Gupta (QUIC) > ; Pradeep Pragallapati (QUIC) > ; Sayali Lokhande (QUIC) > ; Brian Norris ; > Wolfram Sang ; Linus Walleij > > Subject: Re: [PATCH V1 1/2] mmc: core: Define new vendor ops to enable > internal features >=20 > On Fri, Apr 14, 2023 at 06:52:18AM +0000, Sarthak Garg (QUIC) wrote: > > Sorry for the confusion by vendor file I meant driver file for Qualcomm= SDCC > controller (sdhci-msm.c). >=20 > This is still not how we do development. The two series you've been poin= ted out > got valuable feedback that;s been ignored for between one and four years,= that > needs to be followed up with. >=20 > You're not going to get magic hooks for your driver that you're not shari= ng with > us just because you're too lazy to follow up on the review comments.