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Date:   Thu, 11 May 2023 11:45:53 +0200
From:   Maxime Ripard <maxime@cerno.tech>
To:     Dinh Nguyen <dinguyen@kernel.org>
Cc:     Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
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Subject: Re: [PATCH v3 29/65] clk: socfpga: gate: Add a determine_rate hook
Message-ID: <x4xc7kjkphbejmjj35ohlk6u33vshysr4jii4fmu7ogbzrk6zg@2dry3apxjhad>
References: <20221018-clk-range-checks-fixes-v3-0-9a1358472d52@cerno.tech>
 <20221018-clk-range-checks-fixes-v3-29-9a1358472d52@cerno.tech>
 <679921ee-98d4-d6ef-5934-e009fd4b31fc@kernel.org>
 <sjlp5ubnpvulgwhhymmfkmmobkgxacyqwagqozodkee3di2qik@3igj6k3zgbk6>
 <57dd81d0-510e-0fab-670d-1109eb8dd974@kernel.org>
 <tgtfisqxubin4cjj6q26fboirbcnjzcazt5y3m322lw5lskz6l@d3tgz4hdfnk2>
 <1b766164-b5e8-61ac-bf73-6d2c49c72409@kernel.org>
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Hi Dinh,

On Tue, May 09, 2023 at 12:37:39PM -0500, Dinh Nguyen wrote:
> Hi Maxime,
>=20
> On 5/4/23 12:04, Maxime Ripard wrote:
> > Hi Dinh,
> >=20
> > On Thu, Apr 27, 2023 at 02:09:48PM -0500, Dinh Nguyen wrote:
> > > Hi Maxime,
> > >=20
> > > On 4/25/23 09:48, Maxime Ripard wrote:
> > > > Hi Dinh,
> > > >=20
> > > > On Mon, Apr 24, 2023 at 01:32:28PM -0500, Dinh Nguyen wrote:
> > > > > On 4/4/23 05:11, Maxime Ripard wrote:
> > > > > > The SoCFGPA gate clock implements a mux with a set_parent hook,=
 but
> > > > > > doesn't provide a determine_rate implementation.
> > > > > >=20
> > > > > > This is a bit odd, since set_parent() is there to, as its name =
implies,
> > > > > > change the parent of a clock. However, the most likely candidat=
e to
> > > > > > trigger that parent change is a call to clk_set_rate(), with
> > > > > > determine_rate() figuring out which parent is the best suited f=
or a
> > > > > > given rate.
> > > > > >=20
> > > > > > The other trigger would be a call to clk_set_parent(), but it's=
 far less
> > > > > > used, and it doesn't look like there's any obvious user for tha=
t clock.
> > > > > >=20
> > > > > > So, the set_parent hook is effectively unused, possibly because=
 of an
> > > > > > oversight. However, it could also be an explicit decision by the
> > > > > > original author to avoid any reparenting but through an explici=
t call to
> > > > > > clk_set_parent().
> > > > > >=20
> > > > > > The latter case would be equivalent to setting the flag
> > > > > > CLK_SET_RATE_NO_REPARENT, together with setting our determine_r=
ate hook
> > > > > > to __clk_mux_determine_rate(). Indeed, if no determine_rate
> > > > > > implementation is provided, clk_round_rate() (through
> > > > > > clk_core_round_rate_nolock()) will call itself on the parent if
> > > > > > CLK_SET_RATE_PARENT is set, and will not change the clock rate
> > > > > > otherwise. __clk_mux_determine_rate() has the exact same behavi=
or when
> > > > > > CLK_SET_RATE_NO_REPARENT is set.
> > > > > >=20
> > > > > > And if it was an oversight, then we are at least explicit about=
 our
> > > > > > behavior now and it can be further refined down the line.
> > > > > >=20
> > > > > > Signed-off-by: Maxime Ripard <maxime@cerno.tech>
> > > > > > ---
> > > > > >     drivers/clk/socfpga/clk-gate.c | 3 ++-
> > > > > >     1 file changed, 2 insertions(+), 1 deletion(-)
> > > > > >=20
> > > > > > diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfp=
ga/clk-gate.c
> > > > > > index 32ccda960f28..cbba8462a09e 100644
> > > > > > --- a/drivers/clk/socfpga/clk-gate.c
> > > > > > +++ b/drivers/clk/socfpga/clk-gate.c
> > > > > > @@ -110,6 +110,7 @@ static unsigned long socfpga_clk_recalc_rat=
e(struct clk_hw *hwclk,
> > > > > >     static struct clk_ops gateclk_ops =3D {
> > > > > >     	.recalc_rate =3D socfpga_clk_recalc_rate,
> > > > > > +	.determine_rate =3D __clk_mux_determine_rate,
> > > > > >     	.get_parent =3D socfpga_clk_get_parent,
> > > > > >     	.set_parent =3D socfpga_clk_set_parent,
> > > > > >     };
> > > > > > @@ -166,7 +167,7 @@ void __init socfpga_gate_init(struct device=
_node *node)
> > > > > >     	init.name =3D clk_name;
> > > > > >     	init.ops =3D ops;
> > > > > > -	init.flags =3D 0;
> > > > > > +	init.flags =3D CLK_SET_RATE_NO_REPARENT;
> > > > > >     	init.num_parents =3D of_clk_parent_fill(node, parent_name,=
 SOCFPGA_MAX_PARENTS);
> > > > > >     	if (init.num_parents < 2) {
> > > > > >=20
> > > > >=20
> > > > > This patch broke SoCFPGA boot serial port. The characters are man=
gled.
> > > >=20
> > > > Do you have any other access to that board? If so, could you dump
> > > > clk_summary in debugfs with and without that patch?
> > > >=20
> > >=20
> > > That dump from the clk_summary are identical for both cases.
> >=20
> > Thanks for testing
> >=20
> > I'm a bit confused, there should be no difference in behaviour, and if
> > there was any difference I would expect the clock tree to be somewhat
> > different.
> >=20
> > Could you still paste the clk_summary (and dmesg) output? Which UART
> > driver is being used?
> >=20
> > Also, is there a way for me to test it somehow?
> >=20
>=20
> Apologies, but there is a diff with/without this patch:
>=20
> With patch:
> <           l4_sp_clk                   3        3        0   100000000
> 0     0  50000         ?
> ---
> Without patch:
> >           l4_sp_clk                   4        4        0   100000000
> 0     0  50000         ?
>=20
> The enable/prepare count is 4 instead of 3 in the case of a working UART.
> The debug uart is using the lp_sp_clk.

This is pretty weird, the enable count shouldn't change, really, we're
only changing something in the rate rounding path... Is it using the
snps,dw-apb-uart driver?

Nothing shows up in dmesg?

> The Cyclone5 devkits are pretty cheap if you want to get one.

Are you talking about the DE10-Nano? It seems out of stock everywhere in
Europe :/

Thanks!
Maxime

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