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Date:   Thu, 11 May 2023 20:21:07 +0100
From:   Conor Dooley <conor@kernel.org>
To:     Peter De Schrijver <pdeschrijver@nvidia.com>
Cc:     thierry.reding@gmail.com, jonathanh@nvidia.com, robh+dt@kernel.org,
        krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
        devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
        linux-kernel@vger.kernel.org, stefank@nvidia.com
Subject: Re: [PATCH v4 4/6] dt-bindings: Add support for DRAM MRQ GSCs
Message-ID: <20230511-carnivore-legend-17206803d713@spud>
References: <20230511132048.1122075-1-pdeschrijver@nvidia.com>
 <20230511132048.1122075-5-pdeschrijver@nvidia.com>
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On Thu, May 11, 2023 at 04:20:49PM +0300, Peter De Schrijver wrote:
> Add bindings for DRAM MRQ GSC support.
>=20
> Co-developed-by: Stefan Kristiansson <stefank@nvidia.com>
> Signed-off-by: Stefan Kristiansson <stefank@nvidia.com>
> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>

Perhaps Krzysztof will disagree, but looks fine to me, with some minor
remarks below.
Just to note, I didn't get the cover letter & therefore didn't get the
changelog :/
I know you had a back and forth with him about that, *my* =E2=82=AC0.02 is =
that
either you put the changelog in the cover & send it to everyone, or you
put it in each patch.

> ---
>  .../nvidia,tegra264-bpmp-shmem.yaml           | 47 +++++++++++++++++++
>  1 file changed, 47 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/reserved-memory/nvi=
dia,tegra264-bpmp-shmem.yaml
>=20
> diff --git a/Documentation/devicetree/bindings/reserved-memory/nvidia,teg=
ra264-bpmp-shmem.yaml b/Documentation/devicetree/bindings/reserved-memory/n=
vidia,tegra264-bpmp-shmem.yaml
> new file mode 100644
> index 000000000000..4087459c01db
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-b=
pmp-shmem.yaml
> @@ -0,0 +1,47 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra264-bpmp-=
shmem.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Tegra CPU-NS - BPMP IPC reserved memory
> +
> +maintainers:
> +  - Peter De Schrijver <pdeschrijver@nvidia.com>
> +
> +description: |

You don't appear to have any formatting to preserve, so the | is not
needed.

> +  Define a memory region used for communication between CPU-NS and BPMP.
> +  Typically this node is created by the bootloader as the physical addre=
ss
> +  has to be known to both CPU-NS and BPMP for correct IPC operation.
> +  The memory region is defined using a child node under /reserved-memory.
> +  The sub-node is named shmem@<address>.
> +
> +allOf:
> +  - $ref: reserved-memory.yaml
> +
> +properties:
> +  compatible:
> +    const: nvidia,tegra264-bpmp-shmem
> +
> +  reg:
> +    description: The physical address and size of the shared SDRAM region
> +
> +unevaluatedProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - no-map
> +
> +examples:
> +  - |
> +    reserved-memory {
> +       #address-cells =3D <2>;
> +       #size-cells =3D <2>;

You also do not need these size/address-cells, because...

> +       dram_cpu_bpmp_mail: shmem@f1be0000  {
(nit: double space                          ^^)

> +           compatible =3D "nvidia,tegra264-bpmp-shmem";
> +           reg =3D <0x0 0xf1be0000 0x0 0x2000>;

=2E..the 64-bit registers here are both 0x0.

With those fixed:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Cheers,
Conor.

> +           no-map;
> +       };
> +    };
> +...
> --=20
> 2.34.1
>=20

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