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Date:   Fri, 12 May 2023 07:47:13 +0100
From:   Conor Dooley <conor.dooley@microchip.com>
To:     Xingyu Wu <xingyu.wu@starfivetech.com>
CC:     <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
        Michael Turquette <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
        Philipp Zabel <p.zabel@pengutronix.de>,
        Conor Dooley <conor@kernel.org>,
        Emil Renner Berthing <kernel@esmil.dk>,
        Rob Herring <robh+dt@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Hal Feng <hal.feng@starfivetech.com>,
        William Qiu <william.qiu@starfivetech.com>,
        <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v4 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock
 inputs
Message-ID: <20230512-uproar-external-49a9e793fbc4@wendy>
References: <20230512022036.97987-1-xingyu.wu@starfivetech.com>
 <20230512022036.97987-4-xingyu.wu@starfivetech.com>
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On Fri, May 12, 2023 at 10:20:32AM +0800, Xingyu Wu wrote:
> Add PLL clock inputs from PLL clock generator.
>=20
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> ---
>  .../clock/starfive,jh7110-syscrg.yaml         | 20 +++++++++++++++++--
>  1 file changed, 18 insertions(+), 2 deletions(-)

/tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive=
-2-v1.3b.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed=
, one must be fixed:
	[[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short
	From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-sysc=
rg.yaml
/tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive=
-2-v1.3b.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional f=
ailed, one must be fixed:
	['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_l=
rck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too=
 short
	'i2stx_bclk_ext' was expected
	'i2stx_lrck_ext' was expected
	'i2srx_bclk_ext' was expected
	'i2srx_lrck_ext' was expected
	'tdm_ext' was expected
	'mclk_ext' was expected
	'pll0_out' was expected
	From schema: /Documentation/devicetree/bindings/clock/starfive,jh7110-sysc=
rg.yaml
/tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive=
-2-v1.2a.dtb: clock-controller@13020000: clocks: 'oneOf' conditional failed=
, one must be fixed:
	[[19], [20], [21], [22], [23], [24], [25], [26], [27]] is too short
	From schema: Documentation/devicetree/bindings/clock/starfive,jh7110-syscr=
g.yaml
/tmp/tmp.KDlzwQM5ma/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive=
-2-v1.2a.dtb: clock-controller@13020000: clock-names: 'oneOf' conditional f=
ailed, one must be fixed:
	['osc', 'gmac1_rmii_refin', 'gmac1_rgmii_rxin', 'i2stx_bclk_ext', 'i2stx_l=
rck_ext', 'i2srx_bclk_ext', 'i2srx_lrck_ext', 'tdm_ext', 'mclk_ext'] is too=
 short
	'i2stx_bclk_ext' was expected
	'i2stx_lrck_ext' was expected
	'i2srx_bclk_ext' was expected
	'i2srx_lrck_ext' was expected
	'tdm_ext' was expected
	'mclk_ext' was expected
	'pll0_out' was expected
	Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml

This binding change is incompatible with the existing devicetrees for
the visionfive 2.

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