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Message-ID: <0463378b-60d8-ee05-2a2e-1e709b882bae@starfivetech.com>
Date:   Fri, 12 May 2023 15:15:50 +0800
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Subject: Re: [PATCH v4 7/7] riscv: dts: starfive: jh7110: Add PLL clock node
 and modify syscrg node
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To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Conor Dooley <conor@kernel.org>
CC:     <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
        "Michael Turquette" <mturquette@baylibre.com>,
        Stephen Boyd <sboyd@kernel.org>,
        "Philipp Zabel" <p.zabel@pengutronix.de>,
        Emil Renner Berthing <kernel@esmil.dk>,
        "Rob Herring" <robh+dt@kernel.org>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        "Hal Feng" <hal.feng@starfivetech.com>,
        William Qiu <william.qiu@starfivetech.com>,
        <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
References: <20230512022036.97987-1-xingyu.wu@starfivetech.com>
 <20230512022036.97987-8-xingyu.wu@starfivetech.com>
 <c432c26b-27d3-80dc-fe6b-457996234871@linaro.org>
From:   Xingyu Wu <xingyu.wu@starfivetech.com>
In-Reply-To: <c432c26b-27d3-80dc-fe6b-457996234871@linaro.org>
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On 2023/5/12 14:37, Krzysztof Kozlowski wrote:
> On 12/05/2023 04:20, Xingyu Wu wrote:
>> Add the PLL clock node for the Starfive JH7110 SoC and
>> modify the SYSCRG node to add PLL clocks input.
> 
> 
>> @@ -465,6 +469,12 @@ syscrg: clock-controller@13020000 {
>>  		sys_syscon: syscon@13030000 {
>>  			compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
>>  			reg = <0x0 0x13030000 0x0 0x1000>;
>> +
>> +			pllclk: clock-controller {
>> +				compatible = "starfive,jh7110-pll";
>> +				clocks = <&osc>;
>> +				#clock-cells = <1>;
> 
> This should be part of previous patch. You just added that node. Don't
> add half of devices but entire device.
> 

So do I merge the patch 6 and patch 7 into one patch and add syscon and
clock-controller together?

Best regards,
Xingyu Wu