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([2a02:810d:15c0:828:7ede:fc7b:2328:3883]) by smtp.gmail.com with ESMTPSA id gz20-20020a170907a05400b0095342bfb701sm5115319ejc.16.2023.05.12.00.22.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 12 May 2023 00:22:41 -0700 (PDT) Message-ID: <72c8f49e-ad3e-9241-f2dc-cd523ea19d14@linaro.org> Date: Fri, 12 May 2023 09:22:40 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH v4 7/7] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node Content-Language: en-US To: Xingyu Wu , Conor Dooley Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Michael Turquette , Stephen Boyd , Philipp Zabel , Emil Renner Berthing , Rob Herring , Paul Walmsley , Palmer Dabbelt , Albert Ou , Hal Feng , William Qiu , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org References: <20230512022036.97987-1-xingyu.wu@starfivetech.com> <20230512022036.97987-8-xingyu.wu@starfivetech.com> <0463378b-60d8-ee05-2a2e-1e709b882bae@starfivetech.com> From: Krzysztof Kozlowski In-Reply-To: <0463378b-60d8-ee05-2a2e-1e709b882bae@starfivetech.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,NICE_REPLY_A,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/05/2023 09:15, Xingyu Wu wrote: > On 2023/5/12 14:37, Krzysztof Kozlowski wrote: >> On 12/05/2023 04:20, Xingyu Wu wrote: >>> Add the PLL clock node for the Starfive JH7110 SoC and >>> modify the SYSCRG node to add PLL clocks input. >> >> >>> @@ -465,6 +469,12 @@ syscrg: clock-controller@13020000 { >>> sys_syscon: syscon@13030000 { >>> compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd"; >>> reg = <0x0 0x13030000 0x0 0x1000>; >>> + >>> + pllclk: clock-controller { >>> + compatible = "starfive,jh7110-pll"; >>> + clocks = <&osc>; >>> + #clock-cells = <1>; >> >> This should be part of previous patch. You just added that node. Don't >> add half of devices but entire device. >> > > So do I merge the patch 6 and patch 7 into one patch and add syscon and > clock-controller together? I am okay with adding users of clocks in separate patch, but the clock controller - so part of SYS - should be added when adding SYS. Best regards, Krzysztof