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Fri, 12 May 2023 12:21:58 +0000 Received: from pps.filterd (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 34CCLl6U029029; Fri, 12 May 2023 12:21:55 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 3qdy59u1w2-1; Fri, 12 May 2023 12:21:55 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 34CCLrGg029088; Fri, 12 May 2023 12:21:55 GMT Received: from hu-maiyas-hyd.qualcomm.com (hu-kbajaj-hyd.qualcomm.com [10.147.247.189]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 34CCLsZR029100; Fri, 12 May 2023 12:21:55 +0000 Received: by hu-maiyas-hyd.qualcomm.com (Postfix, from userid 2340697) id 6C91152974D; Fri, 12 May 2023 17:51:54 +0530 (+0530) From: Komal Bajaj To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Srinivas Kandagatla , Conor Dooley Cc: Komal Bajaj , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: [PATCH v3 09/10] arm64: dts: qcom: qdu1000: Add LLCC/system-cache-controller Date: Fri, 12 May 2023 17:51:33 +0530 Message-Id: <20230512122134.24339-10-quic_kbajaj@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230512122134.24339-1-quic_kbajaj@quicinc.com> References: <20230512122134.24339-1-quic_kbajaj@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: EwA_MWar3uiNsoXXrIxDCldGOtP_CnXI X-Proofpoint-GUID: EwA_MWar3uiNsoXXrIxDCldGOtP_CnXI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-12_08,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 mlxscore=0 suspectscore=0 bulkscore=0 phishscore=0 adultscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=533 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305120103 X-Spam-Status: No, score=-2.5 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,T_SCC_BODY_TEXT_LINE, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add a DT node for Last level cache (aka. system cache) controller which provides control over the last level cache present on QDU1000 and QRU1000 SoCs. Signed-off-by: Komal Bajaj --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index ff21e7a6b312..3c557ca27500 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1322,6 +1322,22 @@ #interconnect-cells = <2>; }; + system-cache-controller@19200000 { + compatible = "qcom,qdu1000-llcc"; + reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, + <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, + <0 0x19a00000 0 0x80000>, <0 0x19b00000 0 0x80000>, + <0 0x19e00000 0 0x80000>, <0 0x19f00000 0 0x80000>, + <0 0x1a200000 0 0x80000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc4_base", "llcc5_base", + "llcc6_base", "llcc7_base", "llcc_broadcast_base"; + interrupts = ; + + nvmem-cell-names = "multi_chan_ddr"; + nvmem-cells = <&multi_chan_ddr>; + }; + qfprom: efuse@221c8000 { compatible = "qcom,qdu1000-qfprom", "qcom,qfprom"; reg = <0 0x221c8000 0 0x1000>; -- 2.17.1