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Message-ID: <3b5d7c3c-164d-0690-c2e8-2c7daec4865c@ti.com>
Date:   Sat, 13 May 2023 23:28:22 +0530
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Subject: Re: [EXTERNAL] Re: [PATCH 3/3] arm64: defconfig: enable J721e PCIe
 controller
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To:     Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
        Tom Joseph <tjoseph@cadence.com>,
        Lorenzo Pieralisi <lpieralisi@kernel.org>,
        Krzysztof Wilczy_ski <kw@linux.com>,
        Rob Herring <robh@kernel.org>,
        Bjorn Helgaas <bhelgaas@google.com>,
        Catalin Marinas <catalin.marinas@arm.com>,
        Will Deacon <will@kernel.org>,
        Bjorn Andersson <quic_bjorande@quicinc.com>,
        Arnd Bergmann <arnd@arndb.de>,
        Geert Uytterhoeven <geert+renesas@glider.be>,
        Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
        "N_colas F . R . A . Prado" <nfraprado@collabora.com>,
        Mark Brown <broonie@kernel.org>,
        Rafa_ Mi_ecki <rafal@milecki.pl>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        Nishanth Menon <nm@ti.com>, Milind Parab <mparab@cadence.com>,
        Swapnil Kashinath Jakhade <sjakhade@cadence.com>
CC:     <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,
        <linux-omap@vger.kernel.org>, achal Verma <a-verma1@ti.com>
References: <20230512070510.1873171-1-a-verma1@ti.com>
 <20230512070510.1873171-4-a-verma1@ti.com>
 <13028434-f68c-cad3-056e-d319c1ec35cf@linaro.org>
From:   "Verma, Achal" <a-verma1@ti.com>
In-Reply-To: <13028434-f68c-cad3-056e-d319c1ec35cf@linaro.org>
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Hello Krzysztof,
On 5/12/2023 12:53 PM, Krzysztof Kozlowski wrote:
> On 12/05/2023 09:05, Achal Verma wrote:
>> Enable Cadence PCIe controller and pci-j721e drivers to be built as
>> kernel modules.
> 
> Why? IOW, who needs them. Please provide rationale in the commit msg. I
> am pretty sure I asked for this...
> 
On TI's J7 SOCs, PCIe is composed of PCIe core from Cadence and TI 
wrapper. It is desired to have J7 PCIe working on upstream kernel by 
default. So to enable this I have pushed these defconfig changes.

BTW, I am planning to hold this change until PCIe code changes (rest of 
the patches in this series) gets merged.

Please let me know if there are more concern to this.
Sorry, for this time.

Thanks,
Achal Verma
> 
> Best regards,
> Krzysztof
>