Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20;
Message-ID: <14ac1391-9ab9-d352-d3b1-ba6caae3d9df@amd.com>
Date:   Mon, 15 May 2023 13:56:25 -0700
User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101
 Thunderbird/91.11.0
Subject: Re: [PATCH 1/2] PCI: pciehp: Add support for OS-First Hotplug and
 AER/DPC
Content-Language: en-US
To:     Lukas Wunner <lukas@wunner.de>
Cc:     linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
        Bjorn Helgaas <bhelgaas@google.com>, oohall@gmail.com,
        Mahesh J Salgaonkar <mahesh@linux.ibm.com>,
        Kuppuswamy Sathyanarayanan 
        <sathyanarayanan.kuppuswamy@linux.intel.com>,
        Yazen Ghannam <yazen.ghannam@amd.com>,
        Fontenot Nathan <Nathan.Fontenot@amd.com>
References: <20221101000719.36828-1-Smita.KoralahalliChannabasappa@amd.com>
 <20221101000719.36828-2-Smita.KoralahalliChannabasappa@amd.com>
 <20221104101536.GA11363@wunner.de>
 <fba22d6b-c225-4b44-674b-2c62306135ed@amd.com>
 <20230510201937.GA11550@wunner.de> <20230511152326.GA16215@wunner.de>
 <579cb233-4827-2d03-56ad-1b807a189ba8@amd.com>
 <20230515193835.GA17526@wunner.de>
From:   Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
In-Reply-To: <20230515193835.GA17526@wunner.de>
Content-Type: text/plain; charset=UTF-8; format=flowed
Content-Transfer-Encoding: 7bit
MIME-Version: 1.0
X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1
X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?B?M3RjcU5XZXlXcWE2RExjTDd1TTR1MmRCaVdLTkFYemJqb0VQNnBFRWlOVHZy?=
 =?utf-8?B?TVpHc2ZqSjJ5bStsTGJTRGllQTVvVDc2TkZhbnJpSWpXK0lSTi85dFRCZk8x?=
 =?utf-8?B?QWk0Um0rVE5DT3cyaGtFL2haaEtoN3d6MWsydnovaE5XMlFsOTZDc2Q4YmZM?=
 =?utf-8?B?dXJpTVlTS0svUnNrTWxCeUNWSDlGeEc1YWxYQmxDWEJxVHRBT3oxWlRXQmtF?=
 =?utf-8?B?TDArUGU4OGNGTGRQeFUzdlRWSFEvN1RhY2p4WVV5bHVQL3grMkxlZzNsMXBG?=
 =?utf-8?B?ZzZ6QjZyczZqYjgrem8zOHgzdU4zZHl4UGhsNkFaTmEzM0VycEp2WUtOOVZy?=
 =?utf-8?B?YVAydmNEa0xJNkd0VEtxTzJrcmRsVHlkK1o3cFBwT25GSURMMmtsL2hSaFpz?=
 =?utf-8?B?NE1La1Y3QyszWkZKUVRRc2Fxb3cwVXFqYVpGMTUrVmRNTXVCZFhFOGNndHph?=
 =?utf-8?B?VWc5M3FJNFJnR3l5dUF0Y09KVGk0ajFQOEpMRmhtdlg4WEQxdmMxbEwveDA1?=
 =?utf-8?B?b1hMOVp0Uy9Cam9QUmFNeTNmWFVDazZJUmZIWXJaU1Z1ZlMxSW9mcUFzczgr?=
 =?utf-8?B?SUFyMk9vbVRtaDVqcW9uVmxsYW1pNzVRMFhlRmRJZU4wVDFIRDFFL3dqZVNJ?=
 =?utf-8?B?Q3lGbmNydXg2QjQwdGFPc0JtYTRRL3JGV1BISjZ0b2xuKzZ0N2lkV2NQWXBo?=
 =?utf-8?B?NXVrSHJhVndJS3B0KyswcllNbUp2NmNwQjdRT1N2K0xka1ZIZmJ5bGRzOXp3?=
 =?utf-8?B?bXMzZThYZDByM1lRQVByQ0lOdFVmc24vMjk3VWFicFFJc2FOdkRhTUVEQzA2?=
 =?utf-8?B?bXJLZENVNHJGcVNwQjR4K0xKVE5JR3Mrby8xNmh3T1ZMSVJwZjFmT3hqYmU5?=
 =?utf-8?B?VTlyNGdDTGJrd0E2N0diYWU2SmJtWWx6SW1xcDk4bXNYRmthb0p0TkVlWW5G?=
 =?utf-8?B?YWRLdDJWUElRTzc0bUY5b3VHUitjVklrZ2RMZ1o2bzhLOVRlb3lJQkoxRzU2?=
 =?utf-8?B?ckd6ZCsvWlp3eWhUQUJ0QjhTODhXMTdWVm5GVVhuRXdCQkhtTEZrM0NkUjRF?=
 =?utf-8?B?RVQ2NE9XcVNMMmhaTllXV1JOZDA0MXFIa1ZpRjNXYXFFcXhzRUhQYnRCVUQy?=
 =?utf-8?B?MUV2d1ZuUkVPd2tTTytmcnVHT253TklmSG9Ea0YrYXZqejJldXdqdERHbVJy?=
 =?utf-8?B?SzdjeG5OL0lLaVlZTDhjeGpXQnpvR0tLeFZnZERvUC9CdnNQVHFBWjM4ZVdZ?=
 =?utf-8?B?UzZtUlROUE8zVjRoak9yU1ZQKzdCMnhObVdlWG1ad2tmVGR1eCtyemJocDBl?=
 =?utf-8?B?UmFGT1FNRTI2L1RlcW9OeXdKQ2tXNnNLOTVjTHFCUDZnNWtQbjI4d0dRWmdU?=
 =?utf-8?B?L2NnOXA5NzA4Z0pEN056TDZWREhnZmpnMDdGUk4zWU1kRnliTDZVR0F4V3Zz?=
 =?utf-8?B?MDEyaXlFMU9tNnJlWDhnc2lOeWkyRUFUYm1qeG00K3M3KzY1b2hhbVBCZzVL?=
 =?utf-8?B?VzM1YjhSNks0K3gzbTNPaGRsdnJHV1Y4Q2FQVDlTTVNaME9iVWNYL0FLT09J?=
 =?utf-8?B?Yko4TFBadjVLZFpjMHdROEEzZ1krN1l1c3hBcWVFQ1UyYll0M0FrcG5wNDFR?=
 =?utf-8?B?Uyt3ajhJdEdyZldJcFR2QnRqRlgwdVlPWW5MY2s0cmx2UzBpWmNtbkFVdHc5?=
 =?utf-8?B?N2p3aVUrRDVPaEYvMUcvMU1iK3llSnRJd0l6amJrQW9HRHVlTm1WS1loY3lQ?=
 =?utf-8?B?eVRBdmNpVHVOU0k5czgzTGozczlnR1hQQVVOa2JxWklPU0dTNUoxcEU5M3BM?=
 =?utf-8?B?QXplS2dQWGpBam94NmEzOVFNd2NRQ3VwNklPdUhCSEg0cTFsRHpQZDZ6OXE0?=
 =?utf-8?B?MkFTOFJ4NnhCMXpvaXpYU3k5RHhuSEUvczlDREJxUDJZN1NjYTh6OXBLSFlq?=
 =?utf-8?B?cXVZZCsvRXM1UmtMQmhBZm1MMlRCYW00Ty9xVzBiMEdmbGl6anhxQzJxYW9v?=
 =?utf-8?B?L2RvTzl0cEU0djRsVXNuSXd2ekVMSm52RElmcExBWTN2SWNidGFyemZDTWpv?=
 =?utf-8?B?L0xlR0xCeU55eEpSTjBMNGhjMzl4TG9vZTJWQTg5b29UaEVEa1lCRzIrUmxm?=
 =?utf-8?B?bXN2OW4zOXZ2Y3dWVjVBa2ZFbmRCdnRnU2tIenNTcUlpYWNqcU81UEdTc1Rk?=
 =?utf-8?Q?sh01Z7nILaEP3+QLpZAYIG8H+y7PhGqFm5UbZAX1RSMa?=
X-OriginatorOrg: amd.com
X-MS-Exchange-CrossTenant-Network-Message-Id: f7752140-1f08-4c13-241a-08db5586d99d
X-MS-Exchange-CrossTenant-AuthSource: BYAPR12MB2869.namprd12.prod.outlook.com
X-MS-Exchange-CrossTenant-AuthAs: Internal
X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 May 2023 20:56:27.0367
 (UTC)
X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted
X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d
X-MS-Exchange-CrossTenant-MailboxType: HOSTED
X-MS-Exchange-CrossTenant-UserPrincipalName: 0fXLnOTP4RvhlYbzLLuwDbPEj3ULYVxolMtt1mqEV5Mt8xVGalrJJ/RzNEUGGgcfdzl+GZY3sKp/J8GbHlJzvw==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8339
X-Spam-Status: No, score=-4.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,
        DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,NICE_REPLY_A,
        RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE,
        T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6
X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on
        lindbergh.monkeyblade.net
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

On 5/15/2023 12:38 PM, Lukas Wunner wrote:
> On Mon, May 15, 2023 at 12:20:42PM -0700, Smita Koralahalli wrote:
>> On 5/11/2023 8:23 AM, Lukas Wunner wrote:
>>> Subject: [PATCH] PCI: pciehp: Disable Surprise Down Error reporting
>>>
[...]
>>
>> I have logged in the status registers after the device is removed in
>> pciehp_handle_presence_or_link_change().
> [...]
>> Section 6.2.3.2.2 in PCIe Spec v6.0 has also mentioned that:
>> "If an individual error is masked when it is detected, its error status bit
>> is still affected, but no error reporting Message is sent to the Root
>> Complex, and the error is not recorded in the Header Log, TLP Prefix Log, or
>> First Error Pointer"..
> 
> Thanks for the thorough testing.  So the error is logged and next time
> a reporting message for a different error is sent to the Root Complex,
> that earlier Surprise Down Error will be seen and you'd get belated
> log messages for it, is that what you're saying?

Yes, thereby confusing user on a false error.
> 
> I guess I could amend the patch to let pciehp unconditionally clear
> the Surprise Down Error Status bit upon a DLLSC event.

OK. First, mask the uncorrected AER status register for surprise down 
during initialization and then clear all status registers 
unconditionally including DPC_RP_PIO and others inside 
pciehp_handle_presence_or_link_change()..?

Could I please know, why do you think masking surprise down during 
initialization would be a better approach than reading surprise down 
error status on a DPC event? Because in both approaches we should be 
however clearing status registers right?

> 
> Does the patch otherwise do what you want, i.e. no irritating messages
> and no extra delay incurred by AER/DPC handling?

no irritating messages and no delay as there is no DPC error logged now.

Thanks,
Smita
> 
> Thanks!
> 
> Lukas