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[209.85.214.177]) by smtp.gmail.com with ESMTPSA id b5-20020a17090a9bc500b002367325203fsm129417pjw.50.2023.05.15.16.12.29 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 15 May 2023 16:12:29 -0700 (PDT) Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-1a950b982d4so773595ad.0 for ; Mon, 15 May 2023 16:12:29 -0700 (PDT) X-Received: by 2002:ac8:5c48:0:b0:3f3:8b28:f0b4 with SMTP id j8-20020ac85c48000000b003f38b28f0b4mr67302qtj.18.1684192327980; Mon, 15 May 2023 16:12:07 -0700 (PDT) MIME-Version: 1.0 References: <20230419225604.21204-1-dianders@chromium.org> <20230419155341.v8.9.I2ef26d1b3bfbed2d10a281942b0da7d9854de05e@changeid> <20230512140051.GA217273@aspen.lan> In-Reply-To: <20230512140051.GA217273@aspen.lan> From: Doug Anderson Date: Mon, 15 May 2023 16:11:56 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v8 09/10] arm64: kgdb: Roundup cpus using IPI as NMI To: Daniel Thompson Cc: Catalin Marinas , Will Deacon , Sumit Garg , Marc Zyngier , Mark Rutland , ito-yuichi@fujitsu.com, kgdb-bugreport@lists.sourceforge.net, Chen-Yu Tsai , Masayoshi Mizuma , Peter Zijlstra , Ard Biesheuvel , "Rafael J . Wysocki" , linux-arm-kernel@lists.infradead.org, Stephen Boyd , Lecopzer Chen , Thomas Gleixner , linux-perf-users@vger.kernel.org, Alexandru Elisei , Masayoshi Mizuma , linux-kernel@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On Fri, May 12, 2023 at 7:00=E2=80=AFAM Daniel Thompson wrote: > > On Wed, Apr 19, 2023 at 03:56:03PM -0700, Douglas Anderson wrote: > > From: Sumit Garg > > > > arm64 platforms with GICv3 or later supports pseudo NMIs which can be > > leveraged to roundup CPUs which are stuck in hard lockup state with > > interrupts disabled that wouldn't be possible with a normal IPI. > > > > So instead switch to roundup CPUs using IPI turned as NMI. And in > > case a particular arm64 platform doesn't supports pseudo NMIs, > > it will switch back to default kgdb CPUs roundup mechanism. > > > > Signed-off-by: Sumit Garg > > Tested-by: Chen-Yu Tsai > > Signed-off-by: Douglas Anderson > > --- > > > > (no changes since v1) > > > > arch/arm64/kernel/ipi_nmi.c | 5 +++++ > > arch/arm64/kernel/kgdb.c | 18 ++++++++++++++++++ > > 2 files changed, 23 insertions(+) > > > > diff --git a/arch/arm64/kernel/ipi_nmi.c b/arch/arm64/kernel/ipi_nmi.c > > index c592e92b8cbf..2adaaf1519e5 100644 > > --- a/arch/arm64/kernel/ipi_nmi.c > > +++ b/arch/arm64/kernel/ipi_nmi.c > > @@ -8,6 +8,7 @@ > > > > #include > > #include > > +#include > > #include > > #include > > > > @@ -45,10 +46,14 @@ bool arch_trigger_cpumask_backtrace(const cpumask_t= *mask, bool exclude_self) > > static irqreturn_t ipi_nmi_handler(int irq, void *data) > > { > > irqreturn_t ret =3D IRQ_NONE; > > + unsigned int cpu =3D smp_processor_id(); > > Does this play nice with CONFIG_DEBUG_PREEMPT? I may have missed > something about the NMI entry but a quick scan of the arm64 > arch_irq_disabled() suggests that debug_smp_processor_id() will issue > warnings at this point... > > Other than I didn't see anything I don't like here. Good question. It seems to, at least on the sc7180-trogdor-based system I tested. Just to confirm, I printed out the values of some of the stuff that's checked. When this function was called, I saw: irqs_disabled() =3D> true raw_local_save_flags() =3D> 0x000000f0 __irqflags_uses_pmr() =3D> 1 The "__irqflags_uses_pmr" is the thing that gets set when we try to enable pseudo-NMIs and they're actually there. That causes us to call __pmr_irqs_disabled_flags() which will compare the flags (0xf0) to GIC_PRIO_IRQON (0xe0). If flags is not the same as GIC_PRIO_IRQON then interrupts are disabled. ...so, assuming I understood everything, I think we're OK. I also tried to see what happened with the whole "fallback to use regular IPIs if we don't have pseudo-NMIs enabled" (AKA patch #10 in this series). In that case, I had: irqs_disabled() =3D> true raw_local_save_flags() =3D> 0x000000c0 __irqflags_uses_pmr() =3D> 0 ...in this case we end up in __daif_irqs_disabled_flags(). That checks to see if the flags (0xc0) has the "I bit" (0x80) set. It is set, so interrupts are disabled. -Doug