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From:   Inochi Amaoto <inochiama@outlook.com>
To:     Peter Zijlstra <peterz@infradead.org>,
        Ingo Molnar <mingo@redhat.com>,
        Arnaldo Carvalho de Melo <acme@kernel.org>,
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Cc:     linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
        linux-riscv@lists.infradead.org,
        Inochi Amaoto <inochiama@outlook.com>
Subject: [PATCH 0/2] perf: add T-HEAD C9xx series cpu support
Date:   Tue, 16 May 2023 10:37:12 +0800
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The T-HEAD C9xx series cpu is a series of riscv CPU IP. As this IP was
proposed before the current riscv event standard. It has a non-standard
events encoding for perf events and unimplemented MARCH and MIMP CSR.
This patch add these events to support C9xx cpus.

AFAIK, at least the following chips used C9xx cpu.

* Allwinner D1 (C906)
* T-HEAD th1520 (C910)
* Sophgo mango (C920)

Inochi Amaoto (2):
  perf tools riscv: Allow get_cpuid return empty MARCH and MIMP
  perf vendor events riscv: add T-HEAD C9xx JSON file

 tools/perf/arch/riscv/util/header.c           |  7 +-
 tools/perf/pmu-events/arch/riscv/mapfile.csv  |  1 +
 .../arch/riscv/t-head/c9xx/cache.json         | 67 ++++++++++++++++++
 .../arch/riscv/t-head/c9xx/firmware.json      | 68 +++++++++++++++++++
 .../arch/riscv/t-head/c9xx/instruction.json   | 22 ++++++
 .../arch/riscv/t-head/c9xx/microarch.json     | 42 ++++++++++++
 6 files changed, 201 insertions(+), 6 deletions(-)
 create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/cache.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/firmware.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/instruction.json
 create mode 100644 tools/perf/pmu-events/arch/riscv/t-head/c9xx/microarch.json

--
2.40.1