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Message-ID: <728c0165-3caa-de09-2493-e7225a78b77a@ti.com>
Date:   Tue, 16 May 2023 12:03:38 +0530
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CC:     Nishanth Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>,
        Tero Kristo <kristo@kernel.org>,
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        <s-vadapalli@ti.com>
Subject: Re: [PATCH] arm64: dts: ti: k3-j7200: correct num-lanes requested for
 PCIe
Content-Language: en-US
To:     Achal Verma <a-verma1@ti.com>
References: <20230516062212.2635948-1-a-verma1@ti.com>
From:   Siddharth Vadapalli <s-vadapalli@ti.com>
In-Reply-To: <20230516062212.2635948-1-a-verma1@ti.com>
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Achal,

On 16/05/23 11:52, Achal Verma wrote:
> From: Matt Ranostay <mranostay@ti.com>
> 
> J7200 has a limited 2x support for PCIe, and the properties should be
> updated as such.

According to J7200 Datasheet at [0], the SoC supports up to x4 PCIe lanes. Could
you please clarify where the lanes are documented to be 2x?

[0]: https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf

> 
> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> Signed-off-by: Achal Verma <a-verma1@ti.com>
> ---
>  arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index ef352e32f19d..5e62b431d6e8 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -729,7 +729,7 @@ pcie1_rc: pcie@2910000 {
>  		device_type = "pci";
>  		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>  		max-link-speed = <3>;
> -		num-lanes = <4>;
> +		num-lanes = <2>;
>  		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>  		clocks = <&k3_clks 240 6>;
>  		clock-names = "fck";
> @@ -757,7 +757,7 @@ pcie1_ep: pcie-ep@2910000 {
>  		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
>  		ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
>  		max-link-speed = <3>;
> -		num-lanes = <4>;
> +		num-lanes = <2>;
>  		power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
>  		clocks = <&k3_clks 240 6>;
>  		clock-names = "fck";

-- 
Regards,
Siddharth.