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Date:   Tue, 16 May 2023 08:16:19 +0100
Message-ID: <87cz30wxto.wl-maz@kernel.org>
From:   Marc Zyngier <maz@kernel.org>
To:     wangwudi <wangwudi@hisilicon.com>
Cc:     <linux-kernel@vger.kernel.org>,
        Thomas Gleixner <tglx@linutronix.de>
Subject: Re: [PATCH] irqchip: gic-v3: Collection table support muti pages
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On Tue, 16 May 2023 03:53:06 +0100,
wangwudi <wangwudi@hisilicon.com> wrote:
>=20
>=20
>=20
> =E5=9C=A8 2023/5/16 9:57, wangwudi =E5=86=99=E9=81=93:
> >=20
> >=20
> > -----=E9=82=AE=E4=BB=B6=E5=8E=9F=E4=BB=B6-----
> > =E5=8F=91=E4=BB=B6=E4=BA=BA: Marc Zyngier [mailto:maz@kernel.org]=20
> > =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2023=E5=B9=B45=E6=9C=8815=E6=97=
=A5 20:45
> > =E6=94=B6=E4=BB=B6=E4=BA=BA: wangwudi <wangwudi@hisilicon.com>
> > =E6=8A=84=E9=80=81: linux-kernel@vger.kernel.org; Thomas Gleixner <tglx=
@linutronix.de>
> > =E4=B8=BB=E9=A2=98: Re: [PATCH] irqchip: gic-v3: Collection table suppo=
rt muti pages
> >=20
> > On Mon, 15 May 2023 13:10:04 +0100,
> > wangwudi <wangwudi@hisilicon.com> wrote:
> >>
> >> Only one page is allocated to the collection table.
> >> Recalculate the page number of collection table based on the number of=
=20
> >> CPUs.
> >=20
> > Please document *why* we should even consider this. Do you know of
> > any existing implementation that is so large (or need so much
> > memory for its collection) that it would result in overflowing the
> > collection table?
>=20
> Each CPU occupies an entry in the collection table. When there are a
> large number of CPUs and only one page of the collection table, some
> CPUs fail to execute ITS-MAPC cmd, and fail to receive LPI
> interrupts.
>=20
> For example, GITS_BASER indicates that the page_size of the
> collection table is 4 KB, the entry size is 16 Bytes, and only 256
> entries can be stored on one page.  When the number of CPUs is more
> than 256(which is common in the SMP system of the server), the
> subsequent CPUs cannot receive the LPI.

You're stating the obvious. My question was whether we were anywhere
close to that limit on any existing, or even planned HW.

> It is noticed by code review, not by on actual HW.

Right. So let me repeat my question: do you of any existing or planned
implementation that is both:

- using a small ITS page size
- having large per-collection memory requirements
- with a potentially large number of CPUs

that would result in CPUs not fitting in the collection table?

Assuming this is the case, is the CPU numbering space so large and
potentially sparse that it would benefit from 2 level tables instead
of a larger single-level table?

Finally, assuming all the above conditions are satisfied, what
actually populates the second level table in your patch? I don't see
anything that does. Which makes me think that it was never properly
tested.

Thanks,

	M.

--=20
Without deviation from the norm, progress is not possible.