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Message-ID: <df1ffa574ca014cf5e23b3482efc5a7f432948af.camel@maquefel.me>
Subject: Re: [PATCH 0/2] perf: add T-HEAD C9xx series cpu support
From:   Nikita Shubin <nikita.shubin@maquefel.me>
To:     Inochi Amaoto <inochiama@outlook.com>,
        Peter Zijlstra <peterz@infradead.org>,
        Ingo Molnar <mingo@redhat.com>,
        Arnaldo Carvalho de Melo <acme@kernel.org>,
        Mark Rutland <mark.rutland@arm.com>,
        Alexander Shishkin <alexander.shishkin@linux.intel.com>,
        Jiri Olsa <jolsa@kernel.org>,
        Namhyung Kim <namhyung@kernel.org>,
        Ian Rogers <irogers@google.com>,
        Adrian Hunter <adrian.hunter@intel.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Palmer Dabbelt <palmer@dabbelt.com>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Nikita Shubin <n.shubin@yadro.com>
Cc:     linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
        linux-riscv@lists.infradead.org
Date:   Tue, 16 May 2023 13:32:20 +0300
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References: <IA1PR20MB49539201E93DE46A9A2A8E74BB799@IA1PR20MB4953.namprd20.prod.outlook.com>
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Hello Inochi Amaoto!

Thank you for your series!

Could you also provide HPM device tree bindings which were used in
OpenSBI for testing in cover letter ?

On Tue, 2023-05-16 at 10:37 +0800, Inochi Amaoto wrote:
> The T-HEAD C9xx series cpu is a series of riscv CPU IP. As this IP
> was
> proposed before the current riscv event standard. It has a non-
> standard
> events encoding for perf events and unimplemented MARCH and MIMP CSR.
> This patch add these events to support C9xx cpus.
>=20
> AFAIK, at least the following chips used C9xx cpu.
>=20
> * Allwinner D1 (C906)
> * T-HEAD th1520 (C910)
> * Sophgo mango (C920)
>=20
> Inochi Amaoto (2):
> =C2=A0 perf tools riscv: Allow get_cpuid return empty MARCH and MIMP
> =C2=A0 perf vendor events riscv: add T-HEAD C9xx JSON file
>=20
> =C2=A0tools/perf/arch/riscv/util/header.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 7 +-
> =C2=A0tools/perf/pmu-events/arch/riscv/mapfile.csv=C2=A0 |=C2=A0 1 +
> =C2=A0.../arch/riscv/t-head/c9xx/cache.json=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=
=C2=A0=C2=A0=C2=A0 | 67
> ++++++++++++++++++
> =C2=A0.../arch/riscv/t-head/c9xx/firmware.json=C2=A0=C2=A0=C2=A0=C2=A0=C2=
=A0 | 68
> +++++++++++++++++++
> =C2=A0.../arch/riscv/t-head/c9xx/instruction.json=C2=A0=C2=A0 | 22 ++++++
> =C2=A0.../arch/riscv/t-head/c9xx/microarch.json=C2=A0=C2=A0=C2=A0=C2=A0 |=
 42 ++++++++++++
> =C2=A06 files changed, 201 insertions(+), 6 deletions(-)
> =C2=A0create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/cache.json
> =C2=A0create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/firmware.json
> =C2=A0create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/instruction.json
> =C2=A0create mode 100644 tools/perf/pmu-events/arch/riscv/t-
> head/c9xx/microarch.json
>=20
> --
> 2.40.1
>=20
>=20
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